发明授权
- 专利标题: Method of performing timing analysis on integrated circuit chips with consideration of process variations
- 专利标题(中): 考虑过程变化对集成电路芯片进行时序分析的方法
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申请号: US12354306申请日: 2009-01-15
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公开(公告)号: US08141025B2公开(公告)日: 2012-03-20
- 发明人: Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
- 申请人: Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 H. Daniel Schnurmann
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/455
摘要:
A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).