公开(公告)号：US08560989B2

公开(公告)日：2013-10-15

申请号：US13311832

申请日：2011-12-06

申请人： Nathan Buck ,  Brian Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Michael H. Wood ,  Vladimir Zolotov

发明人： Nathan Buck ,  Brian Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Michael H. Wood ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/10 ,  G06F2217/62

摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.

摘要翻译： 将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。 该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。 该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。 该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

公开(公告)号：US20100180243A1

公开(公告)日：2010-07-15

申请号：US12354306

申请日：2009-01-15

申请人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).

摘要翻译： 一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。 通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。 到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。 混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

公开(公告)号：US08141025B2

公开(公告)日：2012-03-20

申请号：US12354306

申请日：2009-01-15

申请人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Debjit Sinha ,  Eric A. Foreman ,  Peter A. Habitz ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).

摘要翻译： 一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。 通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。 到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。 混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

公开(公告)号：US20130036395A1

公开(公告)日：2013-02-07

申请号：US13197320

申请日：2011-08-03

申请人： Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

发明人： Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.

摘要翻译： 本发明的方面提供了用于在集成电路中突出松弛的解决方案。 计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。 基于高斯分布，识别高斯分布的截断子集和余数子集。 然后获得表示余数子集和截断子集之间的比率的数据因子。 这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

公开(公告)号：US08458632B2

公开(公告)日：2013-06-04

申请号：US13197320

申请日：2011-08-03

申请人： Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimer Zolotov

发明人： Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimer Zolotov

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.

摘要翻译： 本发明的方面提供了用于在集成电路中突出松弛的解决方案。 计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。 基于高斯分布，识别高斯分布的截断子集和余数子集。 然后获得表示余数子集和截断子集之间的比率的数据因子。 这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

公开(公告)号：US08707233B2

公开(公告)日：2014-04-22

申请号：US13190083

申请日：2011-07-25

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5081

摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

摘要翻译： 提供了适应SSTA相关参数的系统和方法。 该方法包括确定至少两个参数之间的相关性。 该方法还包括基于至少两个参数之间的相关性计算新参数或新参数集。 该方法还包括执行SSTA，使得新参数或新参数集传播到SSTA中。 该方法还包括使用至少两个参数之间的相关性并使用处理器来投影松弛。

公开(公告)号：US20130104092A1

公开(公告)日：2013-04-25

申请号：US13279373

申请日：2011-10-24

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimir Zolotov

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.

摘要翻译： 在统计静态时序分析（SSTA）方法，系统和程序存储装置的实施例中，需要检查的电路块（例如，锁存器，触发器等）的建立时间和保持时间裕度之间的相互依赖关系 确定设置和保持时序约束），同时考虑到多个参数的可能变化（例如，使用变异感知特性技术）。 执行结合电路块的电路的参数化统计静态时序分析（SSTA），以便以统计参数化形式确定电路块的建立和保持时间。 基于设置和保持时间间隔之间的相互依赖性，可以以统计参数化形式确定建立和保持时间约束。 最后，可以根据建立和保持时间约束来检查SSTA期间确定的建立和保持时间，以确定是否违反时间限制，以及在何种程度上。

公开(公告)号：US08468483B2

公开(公告)日：2013-06-18

申请号：US13279373

申请日：2011-10-24

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimir Zolotov

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladimir Zolotov

IPC分类号： G06F9/455

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.

摘要翻译： 在统计静态时序分析（SSTA）方法，系统和程序存储装置的实施例中，需要检查的电路块（例如，锁存器，触发器等）的建立时间和保持时间裕度之间的相互依赖关系 确定设置和保持时序约束），同时考虑到多个参数的可能变化（例如，使用变异感知特性技术）。 执行结合电路块的电路的参数化统计静态时序分析（SSTA），以便以统计参数化形式确定电路块的建立和保持时间。 基于设置和保持时间间隔之间的相互依赖性，可以以统计参数化形式确定建立和保持时间约束。 最后，可以根据建立和保持时间约束来检查SSTA期间确定的建立和保持时间，以确定是否违反时间限制，以及在何种程度上。

公开(公告)号：US09858368B2

公开(公告)日：2018-01-02

申请号：US13182108

申请日：2011-07-13

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

公开(公告)号：US20130018617A1

公开(公告)日：2013-01-17

申请号：US13182108

申请日：2011-07-13

申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue Wang ,  Vladmimir Zolotov

IPC分类号： G06F19/00

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

摘要翻译： 公开了将制造反馈集成到集成电路设计中的解决方案。 在一个实施例中，公开了一种计算机实现的方法，包括：为第一集成电路产品定义可接受的收益率要求; 获取关于第一集成电路产品的制造数据; 对表示第一集成电路产品中的路径的数据执行回归分析，以基于可接受的产量要求和制造数据来定义多个参数设置; 确定与参数设置相关联的投影角以满足可接受的产量要求; 以及基于投影角和多个参数设置来修改第二集成电路产品的设计。