Invention Grant
US08144501B2 Read/write margin improvement in SRAM design using dual-gate transistors
有权
使用双栅极晶体管的SRAM设计中读/写边沿改进
- Patent Title: Read/write margin improvement in SRAM design using dual-gate transistors
- Patent Title (中): 使用双栅极晶体管的SRAM设计中读/写边沿改进
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Application No.: US12345125Application Date: 2008-12-29
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Publication No.: US08144501B2Publication Date: 2012-03-27
- Inventor: Yen-Huei Chen , Jui-Jen Wu
- Applicant: Yen-Huei Chen , Jui-Jen Wu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
An integrated circuit structure includes a static random access memory (SRAM) cell. The SRAM cell includes a pull-up transistor and a pull-down transistor forming an inverter with the pull-up transistor. The pull-down transistor includes a front gate connected to a gate of the pull-up transistor, and a back-gate decoupled from the front gate.
Public/Granted literature
- US20100165707A1 Read/Write Margin Improvement in SRAM Design Using Dual-Gate Transistors Public/Granted day:2010-07-01
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