Invention Grant
- Patent Title: Semiconductor device including insulating layer of cubic system or tetragonal system
- Patent Title (中): 半导体器件包括立方体或四方晶系的绝缘层
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Application No.: US12238822Application Date: 2008-09-26
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Publication No.: US08159012B2Publication Date: 2012-04-17
- Inventor: Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
- Applicant: Jong-cheol Lee , Jun-noh Lee , Ki-vin Im , Ki-yeon Park , Sung-hae Lee , Sang-yeol Kang
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec
- Priority: KR10-2007-0098402 20070928; KR10-2008-0083516 20080826
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
Public/Granted literature
- US20090085160A1 Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System Public/Granted day:2009-04-02
Information query
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