公开(公告)号：US20170133219A1

公开(公告)日：2017-05-11

申请号：US15336901

申请日：2016-10-28

Applicant: Yong-suk Tak ,  Gi-gwan Park ,  Jin-bum Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Tae-jong Lee

Inventor： Yong-suk Tak ,  Gi-gwan Park ,  Jin-bum Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Tae-jong Lee

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  C23C16/50 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  C23C16/455 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/02126 ,  C23C16/30 ,  C23C16/36 ,  C23C16/45523 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28088 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

公开(公告)号：US08847669B2

公开(公告)日：2014-09-30

申请号：US13543262

申请日：2012-07-06

Applicant: Ki Yeon Park ,  Se Young Jang ,  Chul Eun Yun

Inventor： Ki Yeon Park ,  Se Young Jang ,  Chul Eun Yun

IPC: H01L35/00 ,  G05D23/19

CPC classification number: G05D23/1951

Abstract: A method for controlling a temperature of a terminal and a terminal supporting the same are provided. A terminal supporting temperature control includes a temperature sensor for detecting a temperature of the terminal, and a controller for performing at least one of a first throttle procedure including driving the controller with a first preset driving frequency when the temperature of the terminal detected by the temperature sensor is a first preset temperature, and driving the controller with a second driving frequency higher than the first driving frequency when the temperature of the terminal is reduced to a second preset temperature lower than the first preset temperature, and a second throttle procedure including driving the controller with the first preset driving frequency for a first time, and driving the controller with the second driving frequency higher than the first driving frequency for a second time after the first time elapses.

Abstract translation: 提供了一种用于控制终端的温度和支持其的终端的方法。 终端支持温度控制包括用于检测终端的温度的温度传感器，以及控制器，用于当由温度检测到的终端的温度时，执行包括以第一预设驱动频率驱动控制器的第一节流程序中的至少一个 传感器是第一预设温度，并且当端子的温度降低到比第一预设温度低的第二预设温度时，以比第一驱动频率高的第二驱动频率驱动控制器，以及第二节流程序，包括驱动 具有第一预设驱动频率的控制器，并且在第一次经过第二次之后，以比第一驱动频率高的第二驱动频率驱动控制器。

公开(公告)号：US08258064B2

公开(公告)日：2012-09-04

申请号：US12909947

申请日：2010-10-22

Applicant: Jong-cheol Lee ,  Ki-yeon Park ,  Se-hoon Oh ,  Youn-soo Kim

Inventor： Jong-cheol Lee ,  Ki-yeon Park ,  Se-hoon Oh ,  Youn-soo Kim

IPC: H01L21/31 ,  H01L21/283

CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02145 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02208 ,  H01L21/0228 ,  H01L28/40

Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Abstract translation: 提供形成金属硅酸盐层的方法和制造包括金属硅酸盐层的半导体器件的方法，形成金属硅酸盐层的方法包括使用多个硅前体形成金属硅酸盐。 硅前体是其中与硅结合的配体具有相同分子结构的均质硅前体。

公开(公告)号：US20120188114A1

公开(公告)日：2012-07-26

申请号：US13314446

申请日：2011-12-08

Applicant: Ki Yeon PARK ,  Seong Ho YOON ,  Eun Seok HONG

Inventor： Ki Yeon PARK ,  Seong Ho YOON ,  Eun Seok HONG

IPC: H01Q17/00 ,  B32B37/14 ,  B32B37/02

CPC classification number: H01Q17/00 ,  B32B38/08 ,  B32B2305/076 ,  B32B2307/204 ,  B32B2307/208 ,  B32B2315/085 ,  B32B2363/00 ,  B32B2457/00 ,  H05K9/0088

Abstract: A multi layer electromagnetic wave absorber is provided. The absorber includes a surface layer comprising at least one of a dielectric lossy mixture and a magnetic lossy mixture, an absorption layer, laminated on a rear side of the surface layer, comprising: a dielectric lossy mixture having a higher loss than the dielectric lossy mixture for the surface layer, and a magnetic lossy mixture having a higher loss than the magnetic lossy mixture for the surface layer, and a boundary layer, laminated on a rear side of the absorption layer, comprising a conductive material.

Abstract translation: 提供多层电磁波吸收体。 吸收体包括表面层，该表面层包含介电损耗混合物和磁损耗混合物中的至少一种，层压在表面层后侧的吸收层，包括：具有比介电损耗混合物更高损耗的介电损耗混合物 并且具有比用于表面层的磁损耗混合物损失高的磁损耗混合物和层叠在吸收层的后侧上的包含导电材料的边界层。

公开(公告)号：US20120075823A1

公开(公告)日：2012-03-29

申请号：US13223680

申请日：2011-09-01

Applicant: Ki Yeon PARK ,  Tae Sang PARK ,  Min Young PARK ,  Kun Tak KIM

Inventor： Ki Yeon PARK ,  Tae Sang PARK ,  Min Young PARK ,  Kun Tak KIM

IPC: H05K1/14 ,  B23P11/00

CPC classification number: G02F1/1333 ,  G02F1/133351 ,  G02F1/1339 ,  G02F2201/503 ,  G02F2202/28 ,  H01L27/3244 ,  H01L51/524 ,  Y10T29/49002

Abstract: A display panel and a method of manufacturing the same are provided. The display panel includes a plurality of chip panels, each chip panel having an upper surface, a lower surface disposed parallel to the upper surface, a side surface between the upper surface and the lower surface and a connection portion between the side surface and at least one of the upper surface and the lower surface, the connection portion having a rounded configuration, and an adhesive layer interposed between the chip panels in order to vertically stack the chip panels to connect the chip panels. Therefore, in the display panel, the strength of the edge portion can be improved. Also, by forming a connection portion, a stress can be suppressed from being concentrated at the edge portion by an external mechanical stress.

Abstract translation: 提供一种显示面板及其制造方法。 显示面板包括多个芯片面板，每个芯片面板具有上表面，平行于上表面设置的下表面，上表面和下表面之间的侧表面以及至少在侧表面之间的连接部分 上表面和下表面中的一个，连接部分具有圆形构造，以及插入在芯片面板之间的粘合层，以便垂直堆叠芯片面板以连接芯片面板。 因此，在显示面板中，能够提高边缘部的强度。 此外，通过形成连接部分，可以通过外部机械应力来抑制应力在集中在边缘部分。

公开(公告)号：US07800162B2

公开(公告)日：2010-09-21

申请号：US12235689

申请日：2008-09-23

Applicant: Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

Inventor： Sung-hae Lee ,  Ki-yeon Park ,  Min-Kyung Ryu ,  Myoung-bum Lee ,  Jun-noh Lee

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer.

Abstract translation: 非易失性存储器件包括半导体衬底，半导体衬底上的隧道绝缘层，隧道绝缘层上的电荷存储层，电荷存储层上的电极间绝缘层和电极上的控制栅电极 绝缘层。 电极间绝缘层包括具有大于氮化硅的介电常数的高k电介质层，以及电荷存储层和高k电介质层之间的界面层。 界面层包括氧氮化硅层。

公开(公告)号：US20100167554A1

公开(公告)日：2010-07-01

申请号：US12648377

申请日：2009-12-29

Applicant: Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

Inventor： Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

IPC: H01L21/469

CPC classification number: C23C16/4554 ,  C23C16/45531 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L28/60 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract translation: 在形成具有均匀构成材料组成的目标层的方法中，包括第一中心原子和配体的第一前体在物体的第一反应位置被化学吸附。 然后除去配体或第一中心原子以形成第二反应位点。 包括第二中心原子的第二前体然后在第二反应位点被化学吸附。

公开(公告)号：US20090250741A1

公开(公告)日：2009-10-08

申请号：US12457364

申请日：2009-06-09

Applicant: Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

Inventor： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

IPC: H01L29/788

CPC classification number: H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

Abstract: A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

Abstract translation: 提供了具有复合电介质层的半导体器件和/或栅极结构及其制造方法。 在半导体器件中，提供栅极结构和方法，可以在衬底上形成第一导电层。 可以除去形成在第一导电层上的自然氧化物层。 第一导电层的表面可以被氮化，使得表面可以改变为氮化物层。 可以在氮化物层上形成包括第一和/或第二电介质层的复合电介质层。 可以在复合介电层上形成第二导电层。 第一电介质层可以包括具有较高介电常数的材料。 第二电介质层可以抑制第一电介质层的结晶化。

公开(公告)号：US20090127611A1

公开(公告)日：2009-05-21

申请号：US12120443

申请日：2008-05-14

Applicant: Ki-yeon Park ,  Cha-young Yoo ,  Sung-hae Lee ,  Jun-noh Lee ,  Min-kyung Ryu

Inventor： Ki-yeon Park ,  Cha-young Yoo ,  Sung-hae Lee ,  Jun-noh Lee ,  Min-kyung Ryu

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

Abstract: A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.

Abstract translation: 非易失性存储器件包括包括源区和漏区的半导体层和源区和漏区之间的沟道区; 在半导体层的沟道区上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层，并且包括具有第一厚度的第一氧化物层，高k电介质层和具有不同于第一厚度的第二厚度的第二氧化物层，其顺次层叠在电荷存储层上 ; 和阻挡绝缘层上的控制栅极。

公开(公告)号：US07510931B2

公开(公告)日：2009-03-31

申请号：US11605452

申请日：2006-11-29

Applicant: Ki-yeon Park ,  Han-mei Choi ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim

Inventor： Ki-yeon Park ,  Han-mei Choi ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/4763

CPC classification number: H01L29/792 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/66833

Abstract: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas onto the charge trapping layer, forming a second charge blocking layer on the first charge blocking layer by supplying a metal source gas and a second oxidizing gas onto the first charge blocking layer, wherein the second oxidizing gas has a higher oxidizing power as compared to the first oxidizing gas, and forming a gate electrode layer on the second charge blocking layer.

Abstract translation: 一种制造非易失性存储器件的方法包括：在半导体衬底上形成电荷隧穿层，在电荷隧道层上形成电荷俘获层，在电荷俘获层上形成第一电荷阻挡层，通过提供金属源气体和第一 在电荷捕获层上氧化气体，通过在第一电荷阻挡层上提供金属源气体和第二氧化气体，在第一电荷阻挡层上形成第二电荷阻挡层，其中第二氧化气体具有较高的氧化能力， 并且在第二电荷阻挡层上形成栅极电极层。