发明授权
US08161219B2 Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed
有权
用于具有单独布置的总线线路的部分的存储器模块的分布式命令和地址总线架构
- 专利标题： Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed
- 专利标题（中）： 用于具有单独布置的总线线路的部分的存储器模块的分布式命令和地址总线架构
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申请号： US12328690申请日： 2008-12-04
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公开(公告)号： US08161219B2公开(公告)日： 2012-04-17
- 发明人: Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
- 申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
- 申请人地址： DE München
- 专利权人： Qimonda AG
- 当前专利权人： Qimonda AG
- 当前专利权人地址： DE München
- 代理机构： Cozen O'Connor
- 主分类号： G06F13/00
- IPC分类号： G06F13/00
摘要：
Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.
公开/授权文献
- US20100082871A1 Distributed Command and Address Bus Architecture 公开/授权日：2010-04-01
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