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    Condensed memory cell structure using a FinFET
    2.
    发明授权
    Condensed memory cell structure using a FinFET 有权
    使用FinFET的冷凝存储单元结构

    公开(公告)号：US08665629B2

    公开(公告)日：2014-03-04

    申请号：US11864575

    申请日：2007-09-28

    申请人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

    发明人： Human Park ,  Ulrich Klostermann ,  Rainer Leuschner

    IPC分类号： G11C11/00

    CPC分类号： H01L27/228 ,  H01L27/2436 ,  H01L29/66795 ,  H01L29/785

    摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.

    摘要翻译： 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。

    Method for fabrication of crystalline diodes for resistive memories
    3.
    发明授权
    Method for fabrication of crystalline diodes for resistive memories 有权
    制造电阻式存储器晶体二极管的方法

    公开(公告)号：US08637844B2

    公开(公告)日：2014-01-28

    申请号：US13097307

    申请日：2011-04-29

    申请人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

    发明人： Bipin Rajendran ,  Thomas Happ ,  Hsiang-Lan Lung ,  Min Yang

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/8613

    摘要： The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

    摘要翻译： 本发明在一个实施方案中提供了一种制备PN结的方法，所述方法至少包括提供含Si衬底的步骤; 在含Si衬底上形成绝缘层; 通过所述绝缘层形成通孔以露出所述含Si衬底的至少一部分; 形成含Si衬底的暴露部分的种子层; 在至少种子层上形成非晶态Si; 转化至少一部分非晶Si以提供晶体Si; 以及形成邻接所述晶体Si中的第二掺杂区的第一掺杂区。

    Integrated circuit and method for charge reversal of a circuit part of the integrated circuit
    5.
    发明授权
    Integrated circuit and method for charge reversal of a circuit part of the integrated circuit 有权
    用于集成电路电路部分的电荷反转的集成电路和方法

    公开(公告)号：US08629575B2

    公开(公告)日：2014-01-14

    申请号：US12168747

    申请日：2008-07-07

    申请人： Harald Roth ,  Helmut Schneider

    发明人： Harald Roth ,  Helmut Schneider

    IPC分类号： H02J1/00

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  Y10T307/675

    摘要： A description is given of a method for charge reversal of a circuit part of an integrated circuit from a first electrical potential to a second electrical potential of a first voltage network. In this case, the circuit part is connected to the first voltage network for charge reversal. Furthermore, the circuit part is connected to a second voltage network for charge reversal, said second voltage network providing a third electrical potential between the first and the second electrical potential. The circuit part is automatically isolated from the second voltage network before its electrical potential reaches the second electrical potential.

    摘要翻译： 给出了对集成电路的电路部分从第一电压网络的第一电位到第二电位的电荷反转的方法的描述。 在这种情况下，电路部分连接到第一电压网络进行充电反转。 此外，电路部分连接到用于电荷反向的第二电压网络，所述第二电压网络在第一和第二电位之间提供第三电位。 电路部分在其电位达到第二电位之前自动与第二电压网络隔离。

    Integrated circuit including a buried wiring line
    6.
    发明授权
    Integrated circuit including a buried wiring line 有权
    集成电路包括埋地布线

    公开(公告)号：US08618600B2

    公开(公告)日：2013-12-31

    申请号：US12135318

    申请日：2008-06-09

    申请人： Stafan Slesazeck

    发明人： Stafan Slesazeck

    IPC分类号： H01L29/66

    CPC分类号： H01L21/823437 ,  H01L21/743 ,  H01L21/823475 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.

    摘要翻译： 集成电路包括埋地布线留置。 一个实施例提供一种场效应晶体管，其包括掩埋在半导体衬底主表面下方的第一有源区和栅电极。 栅极布线可以埋在主表面下方，并且栅极布线的一部分可以形成栅电极。 在栅极布线之上，形成与第一或第二有源区域相邻且直接接触的埋入接触结构。

    Derivative logical output
    7.
    发明授权
    Derivative logical output 失效
    微分逻辑输出

    公开(公告)号：US08606982B2

    公开(公告)日：2013-12-10

    申请号：US12045369

    申请日：2008-03-10

    申请人： Michael Maldei ,  Petra Stumm

    发明人： Michael Maldei ,  Petra Stumm

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

    摘要： Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.

    摘要翻译： 本发明的实施例涉及使用互连总线在两个设备之间传送数据的方法，系统和制品。 在总线的每个导线上，如果当前位与之前发送的位相同，则传送表示第一逻辑状态的位。 如果当前位不同于紧接在先发送的位，则传送表示第二逻辑状态的位。