Invention Grant
US08161639B2 Method for fabricating an interlayer conducting structure of an embedded circuitry
有权
一种用于制造嵌入式电路的层间导电结构的方法
- Patent Title: Method for fabricating an interlayer conducting structure of an embedded circuitry
- Patent Title (中): 一种用于制造嵌入式电路的层间导电结构的方法
-
Application No.: US12895824Application Date: 2010-09-30
-
Publication No.: US08161639B2Publication Date: 2012-04-24
- Inventor: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
- Applicant: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
- Applicant Address: TW Taoyuan
- Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee: Kinsus Interconnect Technology Corp.
- Current Assignee Address: TW Taoyuan
- Agency: Lin & Associates IP, Inc.
- Priority: TW98134338A 20091009
- Main IPC: H01K3/10
- IPC: H01K3/10

Abstract:
A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
Public/Granted literature
- US20110083323A1 Method For Fabricating An Interlayer Conducting Structure Of An Embedded Circuitry Public/Granted day:2011-04-14
Information query