Invention Grant
US08168496B2 Single die output power stage using trench-gate low-side and LDMOS high-side MOSFETS, structure and method
失效
单晶片输出功率级采用沟槽栅极低边和LDMOS高边MOSFET，结构与方法
- Patent Title: Single die output power stage using trench-gate low-side and LDMOS high-side MOSFETS, structure and method
- Patent Title (中): 单晶片输出功率级采用沟槽栅极低边和LDMOS高边MOSFET，结构与方法
-
Application No.: US12471911Application Date: 2009-05-26
-
Publication No.: US08168496B2Publication Date: 2012-05-01
- Inventor: Francois Hebert
- Applicant: Francois Hebert
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
Public/Granted literature
Information query
IPC分类:
