发明授权
- 专利标题: Cell inferiority test circuit
- 专利标题(中): 电池劣质测试电路
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申请号: US12655312申请日: 2009-12-29
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公开(公告)号: US08184494B2公开(公告)日: 2012-05-22
- 发明人: Joo Hyeon Lee
- 申请人: Joo Hyeon Lee
- 申请人地址: KR Icheon-si
- 专利权人: Hynix Semiconductor Inc.
- 当前专利权人: Hynix Semiconductor Inc.
- 当前专利权人地址: KR Icheon-si
- 代理机构: Cooper & Dunham LLP
- 代理商 John P. White
- 优先权: KR10-2009-0026044 20090326
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.
公开/授权文献
- US20100246292A1 Cell Inferiority test circuit 公开/授权日:2010-09-30
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