-
公开(公告)号：US20100202226A1
公开(公告)日：2010-08-12
申请号：US12459111
申请日：2009-06-26
Applicant: Joo Hyeon Lee
Inventor： Joo Hyeon Lee
CPC classification number: G11C11/4094 , G11C8/12 , G11C11/4076
Abstract: A bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and a bank precharge signal generation unit for receiving the first and second precharge signals and generate first and second bank precharge signals for precharging first and second banks.
Abstract translation: 存储体预充电信号产生电路包括一个预充电信号产生单元，用于产生一个第二预充电信号，该第二预充电信号包括脉冲，该脉冲响应于全频信号产生装置，该脉冲在与第一预充电信号的脉冲相比延迟预定周期的周期中产生， 存储体预充电信号和存储体预充电信号生成单元，用于接收第一和第二预充电信号，并产生用于对第一和第二存储体进行预充电的第一和第二存储体预充电信号。
-
公开(公告)号：US08184494B2
公开(公告)日：2012-05-22
申请号：US12655312
申请日：2009-12-29
Applicant: Joo Hyeon Lee
Inventor： Joo Hyeon Lee
IPC: G11C29/00
CPC classification number: G11C29/40
Abstract: A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.
Abstract translation: 小区劣势测试电路包括：压缩数据发生器，被配置为响应于选择信号压缩所选择的数据，并产生包括关于小区劣势的信息的压缩数据;选通信号延迟器，被配置为将选通信号延迟一个由测试设置的时间量 信号并产生延迟的选通信号，以及输入/输出线驱动器，被配置为与延迟的选通信号同步地接收压缩数据并驱动全局输入/输出线。
-
公开(公告)号：US08036045B2
公开(公告)日：2011-10-11
申请号：US12315025
申请日：2008-11-26
Applicant: Joo Hyeon Lee , Yin Jae Lee
Inventor： Joo Hyeon Lee , Yin Jae Lee
IPC: G11C7/10
CPC classification number: G11C7/1045 , G11C7/1006 , G11C7/1012
Abstract: A data output control circuit in a semiconductor memory device includes a driving signal generating unit configured to decode first and second I/O mode signals and first and second address level signals in response to a bank active signal and generate driving signals, and a data output multiplexing unit configured to output data signals of global I/O lines as multiplexing signals in response to the driving signals.
Abstract translation: 半导体存储器件中的数据输出控制电路包括：驱动信号生成单元，被配置为响应于存储体有效信号来解码第一和第二I / O模式信号以及第一和第二地址电平信号，并产生驱动信号，以及数据输出 复用单元，被配置为响应于驱动信号，将全局I / O线的数据信号作为多路复用信号输出。
-
公开(公告)号：US08033139B2
公开(公告)日：2011-10-11
申请号：US12459111
申请日：2009-06-26
Applicant: Joo Hyeon Lee
Inventor： Joo Hyeon Lee
IPC: G11C7/00
CPC classification number: G11C11/4094 , G11C8/12 , G11C11/4076
Abstract: A bank precharge signal generation circuit includes a precharge signal generation unit for generating a second precharge signal including a pulse, which is generated in a period delayed by a predetermined period as compared to a pulse of a first precharge signal, in response to an all-bank precharge signal, and a bank precharge signal generation unit for receiving the first and second precharge signals and generate first and second bank precharge signals for precharging first and second banks.
Abstract translation: 存储体预充电信号产生电路包括一个预充电信号产生单元，用于产生一个第二预充电信号，该第二预充电信号包括脉冲，该脉冲响应于全频信号产生装置，该脉冲在与第一预充电信号的脉冲相比延迟预定周期的周期中产生， 存储体预充电信号和存储体预充电信号生成单元，用于接收第一和第二预充电信号，并产生用于对第一和第二存储体进行预充电的第一和第二存储体预充电信号。
-
5.发明申请公开(公告)号：US20100085819A1
公开(公告)日：2010-04-08
申请号：US12319063
申请日：2008-12-30
Applicant: Joo Hyeon Lee , Yin Jae Lee
Inventor： Joo Hyeon Lee , Yin Jae Lee
CPC classification number: G11C8/18 , G11C7/1018
Abstract: A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a first and second burst signals, a control signal generating unit for driving in response to the first and second internal clock signals, wherein the control signal generating unit for generating first and second control signals, enable sections of the first and second control signals being controlled according to the first and second burst signals at a read operation or write operation, and a burst termination signal generating unit for generating a burst termination signal in response to the first and second burst signals. The first control signal is disabled in response to the burst termination signal.
Abstract translation: 能够根据突发长度高速执行读写操作的突发长度控制电路和使用该突发长度的半导体存储器件包括：时钟信号产生单元，用于响应于时钟信号产生第一和第二内部时钟信号 第一和第二突发信号，用于响应于第一和第二内部时钟信号而驱动的控制信号产生单元，其中用于产生第一和第二控制信号的控制信号产生单元使第一和第二控制信号的部分根据 在读取操作或写入操作时与第一和第二突发信号相关联，以及突发终止信号产生单元，用于响应于第一和第二突发信号产生突发终止信号。 第一控制信号响应于突发终止信号被禁用。
-
Patent Agency Ranking
6.发明授权公开(公告)号：US08014227B2
公开(公告)日：2011-09-06
申请号：US12319063
申请日：2008-12-30
Applicant: Joo Hyeon Lee , Yin Jae Lee
Inventor： Joo Hyeon Lee , Yin Jae Lee
IPC: G11C8/00
CPC classification number: G11C8/18 , G11C7/1018
Abstract: A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a first and second burst signals, a control signal generating unit for driving in response to the first and second internal clock signals, wherein the control signal generating unit for generating first and second control signals, enable sections of the first and second control signals being controlled according to the first and second burst signals at a read operation or write operation, and a burst termination signal generating unit for generating a burst termination signal in response to the first and second burst signals. The first control signal is disabled in response to the burst termination signal.
Abstract translation: 能够根据突发长度高速执行读写操作的突发长度控制电路和使用该突发长度的半导体存储器件包括：时钟信号产生单元，用于响应于时钟信号产生第一和第二内部时钟信号 第一和第二突发信号，用于响应于第一和第二内部时钟信号而驱动的控制信号产生单元，其中用于产生第一和第二控制信号的控制信号产生单元使第一和第二控制信号的部分根据 在读取操作或写入操作时与第一和第二突发信号相关联，以及突发终止信号产生单元，用于响应于第一和第二突发信号产生突发终止信号。 第一控制信号响应于突发终止信号被禁用。
-
公开(公告)号：US20090327524A1
公开(公告)日：2009-12-31
申请号：US12315025
申请日：2008-11-26
Applicant: Joo Hyeon Lee , Yin Jae Lee
Inventor： Joo Hyeon Lee , Yin Jae Lee
IPC: G06F3/00
CPC classification number: G11C7/1045 , G11C7/1006 , G11C7/1012
Abstract: A data output control circuit in a semiconductor memory device includes a driving signal generating unit configured to decode first and second I/O mode signals and first and second address level signals in response to a bank active signal and generate driving signals, and a data output multiplexing unit configured to output data signals of global I/O lines as multiplexing signals in response to the driving signals.
Abstract translation: 半导体存储器件中的数据输出控制电路包括：驱动信号生成单元，被配置为响应于存储体有效信号来解码第一和第二I / O模式信号以及第一和第二地址电平信号，并产生驱动信号，以及数据输出 复用单元，被配置为响应于驱动信号，将全局I / O线的数据信号作为多路复用信号输出。
-
公开(公告)号：US08358558B2
公开(公告)日：2013-01-22
申请号：US12824882
申请日：2010-06-28
Applicant: Kyong Ha Lee , Joo Hyeon Lee
Inventor： Kyong Ha Lee , Joo Hyeon Lee
IPC: G11C8/00
CPC classification number: G11C11/408 , G11C7/1018 , G11C7/1066 , G11C2207/2227
Abstract: An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode.
Abstract translation: 呈现地址控制电路用于减少写操作模式中的偏斜。 地址控制电路包括读列地址控制电路和写列地址控制电路。 读列地址控制电路被配置为在读操作模式的第一突发时段期间从地址生成读列地址。 写列地址控制电路被配置为在写操作模式的第二突发周期期间从地址生成写列地址。
-
公开(公告)号：US20100246292A1
公开(公告)日：2010-09-30
申请号：US12655312
申请日：2009-12-29
Applicant: Joo Hyeon Lee
Inventor： Joo Hyeon Lee
CPC classification number: G11C29/40
Abstract: A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a strobe signal by an amount of time set by a test signal and to generate a delayed strobe signal, and an input/output line driver configured to receive the compression data in sync with the delayed strobe signal and to drive a global input/output line.
Abstract translation: 小区劣势测试电路包括：压缩数据发生器，被配置为响应于选择信号压缩所选择的数据，并产生包括关于小区劣势的信息的压缩数据;选通信号延迟器，被配置为将选通信号延迟一个由测试设置的时间量 信号并产生延迟的选通信号，以及输入/输出线驱动器，被配置为与延迟的选通信号同步地接收压缩数据并驱动全局输入/输出线。
-
公开(公告)号：US20090261354A1
公开(公告)日：2009-10-22
申请号：US12404871
申请日：2009-03-16
Applicant: Jae-Kook HA , Chang-Woong Chu , Joo Hyeon Lee
Inventor： Jae-Kook HA , Chang-Woong Chu , Joo Hyeon Lee
IPC: H01L33/00
CPC classification number: H01L51/5278 , H01L27/322 , H01L51/5036 , H01L51/5052 , H01L51/5088 , H01L51/5092
Abstract: The present invention relates to an organic light emitting element and an organic light emitting device including the same. An impurity layer close to an electrode is doped with a small amount, and an impurity layer for a p-n junction is doped with a large amount, such that a high current may flow under a low voltage.
Abstract translation: 本发明涉及一种有机发光元件和包括该有机发光元件的有机发光器件。 在电极附近的杂质层被掺杂少量，并且掺杂大量用于p-n结的杂质层，使得高电流可能在低电压下流动。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.012 seconds)
