发明授权
US08187924B2 Method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit
失效
半导体集成电路的方法，设计程序和设计支持装置以及半导体集成电路
- 专利标题： Method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit
- 专利标题（中）： 半导体集成电路的方法，设计程序和设计支持装置以及半导体集成电路
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申请号： US12826235申请日： 2010-06-29
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公开(公告)号： US08187924B2公开(公告)日： 2012-05-29
- 发明人: Yohei Nakajima , Makoto Nonaka
- 申请人： Yohei Nakajima , Makoto Nonaka
- 申请人地址： JP Kanagawa
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Kanagawa
- 代理机构： Sughrue Mion, PLLC
- 优先权： JP2009-179305 20090731
- 主分类号： H01L21/82
- IPC分类号： H01L21/82
摘要：
A design method for a semiconductor integrated circuit, includes: a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area.
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