Invention Grant
- Patent Title: Method of eliminating micro-trenches during spacer etch
- Patent Title (中): 间隔蚀刻时消除微沟槽的方法
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Application No.: US12258366Application Date: 2008-10-24
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Publication No.: US08187950B2Publication Date: 2012-05-29
- Inventor: Ting Cheong Ang
- Applicant: Ting Cheong Ang
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN200810040371 20080708
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers.
Public/Granted literature
- US20100006975A1 METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH Public/Granted day:2010-01-14
Information query
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