A semiconductor device includes an internal source clock generation unit configured to output first and second internal source clocks, a clock phase correction unit configured to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks, a clock delay unit configured to delay the first and second phase-corrected internal source clocks and to generate first and second delay locked loop (DLL) clocks, and a clock output unit configured to mix phases of the first and second DLL clocks to output a DLL clock, and to output a feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.