Invention Grant
- Patent Title: Architecture for efficient usage of IO
- Patent Title (中): 高效使用IO的架构
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Application No.: US12391944Application Date: 2009-02-24
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Publication No.: US08207754B2Publication Date: 2012-06-26
- Inventor: Paras Garg , Saiyid Mohammad Irshad Rizvi
- Applicant: Paras Garg , Saiyid Mohammad Irshad Rizvi
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Seed IP Law Group PLLC
- Main IPC: H03K19/0175
- IPC: H03K19/0175

Abstract:
An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.
Public/Granted literature
- US20100213980A1 ARCHITECTURE FOR EFFICIENT USAGE OF IO Public/Granted day:2010-08-26
Information query
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