Invention Grant
US08207754B2 Architecture for efficient usage of IO 有权
高效使用IO的架构

Architecture for efficient usage of IO
Abstract:
An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.
Public/Granted literature
Information query
Patent Agency Ranking
0/0