发明授权
- 专利标题: Process for improving the reliability of interconnect structures and resulting structure
- 专利标题(中): 提高互连结构和结构结构可靠性的方法
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申请号: US12879770申请日: 2010-09-10
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公开(公告)号: US08212330B2公开(公告)日: 2012-07-03
- 发明人: Hsien-Wei Chen , Jian-Hong Lin , Tzu-Li Lee
- 申请人: Hsien-Wei Chen , Jian-Hong Lin , Tzu-Li Lee
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater & Matsil, L.L.P.
- 主分类号: H01L23/52
- IPC分类号: H01L23/52
摘要:
An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
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