公开(公告)号：US20130063175A1

公开(公告)日：2013-03-14

申请号：US13231812

申请日：2011-09-13

Applicant: Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

Inventor： Bi-Ling Lin ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Lee-Der Chen ,  Jiaw-Ren Shih ,  Chwei-Ching Chiu

IPC: G01R31/26 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L23/5256 ,  G01R31/2853 ,  G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.

Abstract translation: 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

公开(公告)号：US08379365B2

公开(公告)日：2013-02-19

申请号：US12768001

申请日：2010-04-27

Applicant: Chin-Shan Wang ,  Jian-Hong Lin ,  Chien-Jung Wang

Inventor： Chin-Shan Wang ,  Jian-Hong Lin ,  Chien-Jung Wang

IPC: H01G4/005 ,  H01G4/06

CPC classification number: H01L29/92 ,  H01G4/012 ,  H01G4/228 ,  H01G4/30 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.

Abstract translation: 电容器包括包括第一导电线和通孔的第一电极。 同一层上的第一导电线彼此平行并且连接到第一周边导电线。 第一导体线在相邻层中对准并且通过通孔彼此耦合。 电容器还包括与包括第二导电线和通孔的第一电极对准的第二电极。 相同层上的第二导电线彼此平行并连接到第二外围导电线。 第二导体线在相邻层中对准并且通过通孔彼此耦合。 电容器还包括形成在第一电极和第二电极之间的氧化物层。 通孔在布局上具有矩形（槽）形状。 在一个实施例中，导电线和通孔是金属，例如。 铜，铝或钨。

公开(公告)号：US20120146920A1

公开(公告)日：2012-06-14

申请号：US13072803

申请日：2011-03-28

Applicant: Jian-Hong Lin ,  Wen-Rei Guo ,  Ching-Hua Chuang

Inventor： Jian-Hong Lin ,  Wen-Rei Guo ,  Ching-Hua Chuang

IPC: G06F3/041

CPC classification number: G06F3/041 ,  G02F1/13338 ,  G06F3/0412 ,  G06F3/0418

Abstract: A touch panel includes a touch sensor, a liquid crystal panel, and a reverse circuit. The reverse circuit receives common voltage ripples of the liquid crystal panel, and outputs reversed common voltage ripples after reversing the common voltage ripples. After the touch sensor receives the reversed common voltage ripples, the touch sensor outputs a sensing signal according to the reversed common voltage ripples.

Abstract translation: 触摸面板包括触摸传感器，液晶面板和反向电路。 反向电路接收液晶面板的公共电压波纹，并在反转公共电压纹波之后输出反向的公共电压纹波。 在触摸传感器接收到反向的公共电压波纹之后，触摸传感器根据反向的公共电压纹波输出感测信号。

公开(公告)号：US20120002375A1

公开(公告)日：2012-01-05

申请号：US12827742

申请日：2010-06-30

Applicant: Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

Inventor： Jian-Hong LIN ,  Chin Chuan PENG ,  Tzu-Li LEE ,  Bi-Ling LIN ,  Bor-Jou WEI ,  Chien Shih TSAI

IPC: H05K7/20 ,  H01L21/02

CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.

Abstract translation: 一种半导体结构，用于从具有相邻器件和互连的电阻器散热。 半导体结构包括半导体衬底，设置在半导体衬底之上的电阻器和设置在电阻器上方的热保护结构。 热保护结构具有多个散热元件，散热元件的一端设置成与热保护结构导热接触，另一端与半导体衬底导热接触。 热保护结构接收从电阻器产生的热量，并且散热元件将热量散发到半导体衬底。

公开(公告)号：US07893459B2

公开(公告)日：2011-02-22

申请号：US11786076

申请日：2007-04-10

Applicant: Chien-Jung Wang ,  Jian-Hong Lin

Inventor： Chien-Jung Wang ,  Jian-Hong Lin

IPC: H01L29/02

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.

Abstract translation: 半导体芯片包括与半导体芯片的边缘相邻的密封环; 从所述密封环的顶表面延伸到底表面的开口，其中所述开口具有在所述密封环的外侧上的第一端和所述密封环的内侧上的第二端; 以及具有平行于所述密封环的最近侧的侧壁的防潮屏障，其中所述防潮层邻近所述密封环并且具有面向所述开口的部分。

公开(公告)号：US20110025590A1

公开(公告)日：2011-02-03

申请号：US12630852

申请日：2009-12-04

Applicant: Jian-Hong Lin ,  Wei-Cheng Lin

Inventor： Jian-Hong Lin ,  Wei-Cheng Lin

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display device having bi-directional scan mechanism includes a plurality of gate lines, a first shift register circuit and a second shift register circuit. The first shift register circuit includes a plurality of forward shift register stages. The second shift register circuit includes a plurality of backward shift register stages. Each of the gate lines is electrically connected to both a corresponding forward shift register stage and a corresponding backward shift register stage. When the first shift register circuit is enabled, the forward shift register stages are employed to provide plural forward gate signals sequentially enabled for scanning the gate lines based on a first sequence. When the second shift register circuit is enabled, the backward shift register stages are employed to provide plural backward gate signals sequentially enabled for scanning the gate lines based on a second sequence opposite to the first sequence.

Abstract translation: 具有双向扫描机构的显示装置包括多条栅极线，第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路包括多个正向移位寄存器级。 第二移位寄存器电路包括多个反向移位寄存器级。 每个栅极线电连接到相应的正移位寄存器级和相应的反向移位寄存器级。 当第一移位寄存器电路被使能时，采用正向移位寄存器级以提供依次使能的多个正向栅极信号，以便基于第一序列扫描栅极线。 当第二移位寄存器电路被使能时，采用反向移位寄存器级来提供多个反向栅极信号，该反向栅极信号基于与第一序列相反的第二序列而能够扫描栅极线。

公开(公告)号：US20080014741A1

公开(公告)日：2008-01-17

申请号：US11487741

申请日：2006-07-17

Applicant: Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

Inventor： Hsien-Wei Chen ,  Jian-Hong Lin ,  Tzu-Li Lee

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76828 ,  H01L21/76829 ,  H01L2221/1047

Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.

Abstract translation: 提供了具有改善的可靠性的集成电路的互连结构及其形成方法。 该方法包括提供衬底，形成覆盖在衬底上的电介质层，执行第一收缩过程，其中电介质层收缩并具有第一收缩率，在执行第一收缩过程的步骤之后在介电层中形成导电特征 并且在形成导电特征的步骤之后执行第二收缩过程，其中介电层基本上收缩并且具有第二收缩率。

公开(公告)号：US07235424B2

公开(公告)日：2007-06-26

申请号：US11181433

申请日：2005-07-14

Applicant: Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

Inventor： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC: H01L21/00

CPC classification number: H01L21/3212 ,  H01L21/31053

Abstract: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

Abstract translation: 在一个实施例中，本发明涉及一种用于在金属层的稀疏填充部分中插入虚拟图案的方法和装置。 虚拟图案反映了可能导致不均匀的后抛光膜厚度的半导体布局中的图案密度变化的影响。 根据本公开的一个实施例的算法基于金属层中的图案来确定虚拟图案的尺寸和位置，首先以小的虚拟图案围绕金属结构，然后用大的虚拟图案填充任何剩余的空隙。

公开(公告)号：US20070018279A1

公开(公告)日：2007-01-25

申请号：US11186581

申请日：2005-07-21

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 半导体结构防止用于熔断保险丝的能量造成损坏。 半导体结构包括器件，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20060226507A1

公开(公告)日：2006-10-12

申请号：US11091508

申请日：2005-03-29

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.

Abstract translation: 一种用于半导体器件的激光熔丝结构，所述激光熔丝结构具有激光熔丝阵列，其中阵列中的一个或多个熔丝具有在将熔丝连接到下面的电路区域的第一和第二连接器之间延伸的曲折熔丝。