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US08214770B2 Multilayer OPC for design aware manufacturing 有权
多层OPC用于设计感知制造

Multilayer OPC for design aware manufacturing
Abstract:
A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
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