-
公开(公告)号：US08214770B2
公开(公告)日：2012-07-03
申请号：US12357648
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
-
公开(公告)号：US07503028B2
公开(公告)日：2009-03-10
申请号：US11306750
申请日：2006-01-10
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
-
3.发明申请公开(公告)号：US20090125868A1
公开(公告)日：2009-05-14
申请号：US12357648
申请日：2009-01-22
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
-
公开(公告)号：US20070220476A1
公开(公告)日：2007-09-20
申请号：US11306750
申请日：2006-01-10
申请人： Maharaj Mukherjee , James Culp , Lars Liebmann , Scott Mansfield
发明人： Maharaj Mukherjee , James Culp , Lars Liebmann , Scott Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。
-
5.发明申请SYSTEM AND METHOD OF SMOOTHING MASK SHAPES FOR IMPROVED PLACEMENT OF SUB-RESOLUTION ASSIST FEATURES 失效用于改进分层辅助功能放置的掩模形状的系统和方法公开(公告)号：US20050153212A1
公开(公告)日：2005-07-14
申请号：US10707778
申请日：2004-01-12
申请人： Mark Lavin , Lars Liebmann , Scott Mansfield , Maharaj Mukherjee , Zengqin Zhao
发明人： Mark Lavin , Lars Liebmann , Scott Mansfield , Maharaj Mukherjee , Zengqin Zhao
CPC分类号： G03F1/36
摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.
摘要翻译： 公开了一种相对于掩模的预定主要形状提供光学光刻掩模的相关形状的方法。 该方法包括从掩模的预定主要形状生成简化的布局图案。 通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。 然后相对于简化的掩模图案生成相关联的形状。
-
公开(公告)号：US20060166105A1
公开(公告)日：2006-07-27
申请号：US10905822
申请日：2005-01-21
申请人： Lars Liebmann , Zachary Baum
发明人： Lars Liebmann , Zachary Baum
摘要： A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments. The method then includes identifying design features of the second mask design that violate the predetermined manufacturability design rules, and then creating a third mask design derived from the second mask design wherein the mask features of the second mask design that violate the predetermined manufacturability rules are selectively replaced by mask features from the first mask design so that the third mask design meets the predetermined manufacturability design rules. By way of example, the mask features used to assist in projecting critical width segments may comprise alternating phase shifting regions or sub-resolution assist features.
摘要翻译： 一种设计用于在光刻处理中投影集成电路设计的图像的掩模的方法，其中所述集成电路布局具有多个临界宽度的段。 该方法包括通过对准用于辅助将关键宽度段与集成电路设计的临界宽度段相关联的掩模特征来形成第一掩模设计，使得第一掩模设计符合预定的可制造性设计规则，以及通过 将掩模特征与集成电路设计的关键宽度段对准，使得第二掩模设计在临界宽度段的局部区域满足预定的光刻设计规则。 该方法然后包括识别违反预定可制造性设计规则的第二掩模设计的设计特征，然后创建从第二掩模设计导出的第三掩模设计，其中第二掩模设计的掩盖特征违反预定可制造性规则是选择性的 由第一掩模设计的掩模特征代替，使得第三掩模设计符合预定的可制造性设计规则。 作为示例，用于辅助突出关键宽度段的掩模特征可以包括交替的相移区域或子分辨率辅助特征。
-
7.发明申请METHOD OF CONFLICT AVOIDANCE IN FABRICATION OF GATE-SHRINK ALTERNATING PHASE SHIFTING MASKS 失效闸门相互替换相变掩模制造中的冲突避免方法公开(公告)号：US20050175906A1
公开(公告)日：2005-08-11
申请号：US10708055
申请日：2004-02-05
申请人： Lars Liebmann , Ioana Graur
发明人： Lars Liebmann , Ioana Graur
CPC分类号： G03F1/30
摘要： A method of designing a layout of an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of features to be projected using alternating phase shifting segments, including a gate-shrink region of a transistor having a critical width along a length thereof that extends beyond a diffusion region. The method also provides alternating phase shift design rules based on alternating phase shift design parameters comprising minimum phase width, minimum phase-to-phase spacing, and minimum extension of critical width beyond another feature. The method then includes identifying portions of the integrated circuit layout having a critical width feature that violate the alternating phase shift design rules, and reducing the length that the critical width gate-shrink region feature extends beyond the other diffusion region feature to the minimum extension. An alternating phase shifting mask layout is then generated in conformance with the alternating phase shift design rules.
摘要翻译： 一种设计交替相移掩模的布局的方法，用于使用交变相移段来投影具有要投影的多个特征的集成电路设计的图像，所述交变相移段包括沿着沿着具有临界宽度的晶体管的栅极 - 收缩区域 其长度延伸超过扩散区域。 该方法还提供基于交替相移设计参数的交替相移设计规则，其包括最小相位宽度，最小相间间隔以及临界宽度超出另一特征的最小延伸。 该方法然后包括识别具有违反交替相移设计规则的临界宽度特征的集成电路布局的部分，并且减小临界宽度栅 - 收缩区域特征延伸超出另一扩散区域特征到最小延伸的长度。 然后根据交变相移设计规则生成交替的相移掩模布局。
-
公开(公告)号：US5899706A
公开(公告)日：1999-05-04
申请号：US884862
申请日：1997-06-30
申请人： Andreas Kluwe , Lars Liebmann , Frank Prein , Thomas Zell
发明人： Andreas Kluwe , Lars Liebmann , Frank Prein , Thomas Zell
IPC分类号： H01L21/82 , H01L21/8242 , H01L23/528 , H01L27/108
CPC分类号： H01L23/528 , H01L2924/0002 , Y10S438/926
摘要： In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.
摘要翻译： 为了准备蚀刻处理，具有很少或没有图案的区域的半导体芯片和大量图案的区域，将非操作图案添加到具有很少或没有图案的区域，使得整个图案密度在整个芯片上大致相同。
-
公开(公告)号：US20070212863A1
公开(公告)日：2007-09-13
申请号：US11308106
申请日：2006-03-07
申请人： Timothy Brunner , James Culp , Lars Liebmann
发明人： Timothy Brunner , James Culp , Lars Liebmann
IPC分类号： H01L21/467
CPC分类号： H01L21/76895 , H01L21/0274 , H01L21/28035 , H01L21/28123
摘要： A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.
摘要翻译： 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。
-
公开(公告)号：US20070106968A1
公开(公告)日：2007-05-10
申请号：US11164044
申请日：2005-11-08
申请人： James Culp , Lars Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen Runyon , Patrick Williams
发明人： James Culp , Lars Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen Runyon , Patrick Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
摘要翻译： 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.022 秒)
