发明授权
US08217457B1 Electrostatic discharge (ESD) protection device for use with multiple I/O standards
有权
用于多个I / O标准的静电放电(ESD)保护装置
- 专利标题: Electrostatic discharge (ESD) protection device for use with multiple I/O standards
- 专利标题(中): 用于多个I / O标准的静电放电(ESD)保护装置
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申请号: US12272042申请日: 2008-11-17
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公开(公告)号: US08217457B1公开(公告)日: 2012-07-10
- 发明人: Samit Sengupta , Cheng-Hsiung Huang , Wei-Guang Wu
- 申请人: Samit Sengupta , Cheng-Hsiung Huang , Wei-Guang Wu
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ward & Zinna, LLC
- 主分类号: H01L23/62
- IPC分类号: H01L23/62
摘要:
In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.
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