公开(公告)号：US07468617B1

公开(公告)日：2008-12-23

申请号：US11605516

申请日：2006-11-28

申请人： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

发明人： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

IPC分类号： H03K19/094 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

摘要翻译： 一方面，本发明包括一种静电放电（ESD）保护电路，其包括多个输入电路，其中每个输入电路包括串联连接在电源与地之间的第一PMOS和第一NMOS晶体管以及第一和第二反相器 连接到第一PMOS和NMOS晶体管的栅极。 连接到第一NMOS晶体管的栅极的每个反相器包括连接在该栅极和地之间的第二NMOS晶体管，并且第二NMOS晶体管的栅极宽度与第一NMOS晶体管的栅极宽度之比 输入电路基本相同。 在本发明的另一方面，多指栅极晶体管形成在一个导电类型的第一阱中，该第一阱由相同导电类型的第二阱围绕，该第二阱由浅沟槽隔离和一部分 基质。 第二个阱用作第一个阱的抽头，而衬底电流路径的电阻显着增加。 形成该结构的方法是本发明的另一方面。

公开(公告)号：US07408754B1

公开(公告)日：2008-08-05

申请号：US10992591

申请日：2004-11-18

申请人： Hugh Sung-Ki O ,  Chih-Ching Shih ,  Yow-Juang Bill Liu ,  Cheng-Hsiung Huang ,  Wei-Guang Wu ,  Billy Jow-Tai Kwong ,  Yu-Cheng Richard Gao

发明人： Hugh Sung-Ki O ,  Chih-Ching Shih ,  Yow-Juang Bill Liu ,  Cheng-Hsiung Huang ,  Wei-Guang Wu ,  Billy Jow-Tai Kwong ,  Yu-Cheng Richard Gao

IPC分类号： H02H3/20

CPC分类号： H01L27/0262

摘要： The present invention provides an ESD device for protecting thin oxide layers in transistors or capacitors in an integrated circuit. In one embodiment, the ESD device includes a silicon-controlled rectifier (SCR), the SCR including a PNP bipolar transistor and a NPN bipolar transistor. The ESD device further includes first and second trigger devices coupled to the SCR and configured to simultaneously turn on the PNP bipolar transistor and the NPN bipolar transistor in response to an ESD pulse on the ESD device. The base of the NPN bipolar transistor is floating to allow a first external resistor to be connected between the base and emitter of the NPN bipolar transistor. A second external resistor can be connected between the base and emitter of the PNP bipolar transistor.

摘要翻译： 本发明提供一种用于在集成电路中保护晶体管或电容器中的薄氧化物层的ESD装置。 在一个实施例中，ESD器件包括硅控整流器（SCR），SCR包括PNP双极晶体管和NPN双极晶体管。 ESD器件还包括耦合到SCR的第一和第二触发器件，并被配置为响应于ESD器件上的ESD脉冲同时导通PNP双极晶体管和NPN双极晶体管。 NPN双极晶体管的基极是浮置的，以允许第一外部电阻器连接在NPN双极晶体管的基极和发射极之间。 第二个外部电阻可以连接在PNP双极晶体管的基极和发射极之间。

公开(公告)号：US07210081B1

公开(公告)日：2007-04-24

申请号：US10465139

申请日：2003-06-19

申请人： Bruce Euzent ,  Roy Wei-Guang Wu ,  Jeffrey Barton ,  Anil Pannikkat ,  Vadali Mahadev ,  Tomas Jonsson

发明人： Bruce Euzent ,  Roy Wei-Guang Wu ,  Jeffrey Barton ,  Anil Pannikkat ,  Vadali Mahadev ,  Tomas Jonsson

IPC分类号： G01R31/28

CPC分类号： G01R31/2803 ,  G01R31/2818 ,  G01R31/318516

摘要： An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.

摘要翻译： 一种装置执行电子硬件的可靠性评估。 该装置包括一个测试组件。 测试组件包括至少一个可编程逻辑器件（PLD）。 PLD被配置为提供诸如以级联方式耦合的多个反相器的功能的逻辑功能。 该装置还包括耦合到测试组件的信号源。 信号源向测试组件提供刺激信号。 该装置还包括耦合到测试组件的信号监视器。 信号监视器监视由测试组件产生的响应信号。

公开(公告)号：US08217457B1

公开(公告)日：2012-07-10

申请号：US12272042

申请日：2008-11-17

申请人： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

发明人： Samit Sengupta ,  Cheng-Hsiung Huang ,  Wei-Guang Wu

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate. The second well is used as a tap for the first well with a significant increase in the resistance of the substrate current path. A process for forming this structure is a further aspect of the invention.

摘要翻译： 一方面，本发明包括一种静电放电（ESD）保护电路，其包括多个输入电路，其中每个输入电路包括串联连接在电源与地之间的第一PMOS和第一NMOS晶体管以及第一和第二反相器 连接到第一PMOS和NMOS晶体管的栅极。 连接到第一NMOS晶体管的栅极的每个反相器包括连接在该栅极和地之间的第二NMOS晶体管，并且第二NMOS晶体管的栅极宽度与第一NMOS晶体管的栅极宽度之比 输入电路基本相同。 在本发明的另一方面，多指栅极晶体管形成在一个导电类型的第一阱中，该第一阱由相同导电类型的第二阱围绕，该第二阱由浅沟槽隔离和一部分 基质。 第二个阱用作第一个阱的抽头，而衬底电流路径的电阻显着增加。 形成该结构的方法是本发明的另一方面。