Invention Grant
- Patent Title: Dual layer gate dielectrics for non-silicon semiconductor devices
- Patent Title (中): 用于非硅半导体器件的双层栅极电介质
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Application No.: US12646408Application Date: 2009-12-23
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Publication No.: US08227833B2Publication Date: 2012-07-24
- Inventor: Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau
- Applicant: Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
Non-silicon metal-insulator-semiconductor (MIS) devices and methods of forming the same. The non-silicon MIS device includes a gate dielectric stack which comprises at least two layers of non-native oxide or nitride material. The first material layer of the gate dielectric forms an interface with the non-silicon semiconductor surface and has a lower dielectric constant than a second material layer of the gate dielectric. In an embodiment, a dual layer including a first metal silicate layer and a second oxide layer provides both a good quality oxide-semiconductor interface and a high effective gate dielectric constant.
Public/Granted literature
- US20110147710A1 DUAL LAYER GATE DIELECTRICS FOR NON-SILICON SEMICONDUCTOR DEVICES Public/Granted day:2011-06-23
Information query
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