Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US12969952Application Date: 2010-12-16
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Publication No.: US08227909B2Publication Date: 2012-07-24
- Inventor: Hideaki Sakaguchi , Mitsutoshi Higashi , Yuichi Taguchi , Akinori Shiraishi , Kei Murayama
- Applicant: Hideaki Sakaguchi , Mitsutoshi Higashi , Yuichi Taguchi , Akinori Shiraishi , Kei Murayama
- Applicant Address: JP Nagano-shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2009-291631 20091224
- Main IPC: H01L23/04
- IPC: H01L23/04

Abstract:
There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.
Public/Granted literature
- US20110156242A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2011-06-30
Information query
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