发明授权
US08227916B2 Package structure and method for reducing dielectric layer delamination
有权
用于减少介电层分层的封装结构和方法
- 专利标题： Package structure and method for reducing dielectric layer delamination
- 专利标题（中）： 用于减少介电层分层的封装结构和方法
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申请号： US12757440申请日： 2010-04-09
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公开(公告)号： US08227916B2公开(公告)日： 2012-07-24
- 发明人: Hsiu-Ping Wei , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Tzuan-Horng Liu
- 申请人： Hsiu-Ping Wei , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Tzuan-Horng Liu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 代理机构： Lowe Hauptman Ham & Berner, LLP
- 主分类号： H01L23/498
- IPC分类号： H01L23/498 ; H01L21/3205
摘要：
A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.