公开(公告)号：US09313557B1

公开(公告)日：2016-04-12

申请号：US13558730

申请日：2012-07-26

Applicant: Angela Ying-Ju Chen ,  William Dailey

Inventor： Angela Ying-Ju Chen ,  William Dailey

IPC: A47F7/00 ,  H04Q1/06 ,  G02B6/44

CPC classification number: H04Q1/06 ,  G02B6/4452 ,  H04Q1/09

Abstract: Aspects of the disclosure relate generally to rack systems for housing computing devices. The rack may include a plurality of removable shelves. A removable shelf may include a column having a plurality of slots. By stacking a plurality of the removable shelves in the rack, a larger column may be formed. This larger column may provide additional space to mount other features. In one example, the larger column may be used to mount a wire duct. The wire duct may be attached to a mounting plate having a plurality of hooks. The hooks of the mounting plate may mate with the slots of the columns of the shelves. The mounting plates may be used to mount features at other locations on the rack as well.

Abstract translation: 本公开的方面通常涉及用于外壳计算设备的机架系统。 机架可以包括多个可移除的架子。 可拆卸的搁架可以包括具有多个狭槽的列。 通过将多个可移除的搁架堆叠在架子中，可以形成较大的列。 这个较大的列可以提供额外的空间来安装其他功能。 在一个示例中，较大的柱可用于安装导线管。 导线管可以附接到具有多个钩的安装板。 安装板的钩子可以与架子的列的槽口配合。 安装板也可用于将功能安装在机架上的其他位置。

公开(公告)号：US09208222B2

公开(公告)日：2015-12-08

申请号：US13301192

申请日：2011-11-21

Applicant: David Folchi ,  Ying-Ju Chen

Inventor： David Folchi ,  Ying-Ju Chen

IPC: G06F17/30

CPC classification number: G06F17/30716 ,  G06F17/30551

Abstract: Note management methods and systems are provided. First, inputs are received along a timeline, and at least one note is generated according to the inputs. The at least one note is recorded and arranged along the timeline. In some embodiments, a thumbnail is generated for a respective predefined interval on the timeline according to the at least one note in the respective predefined interval, and the thumbnail of the respective predefined interval is displayed along the timeline.

Abstract translation: 备注管理方法和系统。 首先，沿着时间线接收输入，并且根据输入生成至少一个音符。 至少一个音符沿时间轴记录和排列。 在一些实施例中，根据相应预定义间隔中的至少一个音符，在时间线上针对相应的预定义间隔生成缩略图，并且沿着时间线显示相应预定义间隔的缩略图。

公开(公告)号：US09105588B2

公开(公告)日：2015-08-11

申请号：US12909458

申请日：2010-10-21

Applicant: Ying-Ju Chen ,  Hsien-Wei Chen

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/3205

CPC classification number: H01L23/3171 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2924/01019 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00

Abstract: A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Abstract translation: 公开了半导体部件上的导电特征。 在衬底上形成第一钝化层。 在第一钝化层上形成接合焊盘。 第二钝化层覆盖第一钝化层和接合焊盘。 第二钝化层具有覆盖接合焊盘的第一开口和暴露第一钝化层的顶表面的多个第二开口。 缓冲层覆盖在第二钝化层上并填充多个第二开口。 缓冲层具有与第一开口重叠的第三开口并且一起暴露接合焊盘的一部分。 组合的第一开口和第三开口具有侧壁。 凸块下金属（UBM）层覆盖在组合的第一开口和第三开口的侧壁上，并且与接合焊盘的暴露部分接触。 导电特征覆盖在UBM层上。

公开(公告)号：US08952530B2

公开(公告)日：2015-02-10

申请号：US13618382

申请日：2012-09-14

Applicant: Hsien-Wei Chen ,  Ying-Ju Chen

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/498

CPC classification number: H01L24/14 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05569 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract translation: 一种器件包括金属焊盘，与金属焊盘的边缘部分重叠的钝化层以及钝化层上的第一聚合物层。 后钝化互连（PPI）具有覆盖第一聚合物层的水平部分和具有连接到水平部分的顶部的插头部分。 插头部分延伸到第一聚合物层中。 插头部分的底表面与电介质材料接触。 第二聚合物层覆盖第一聚合物层。

公开(公告)号：US08618827B2

公开(公告)日：2013-12-31

申请号：US12903984

申请日：2010-10-13

Applicant: Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

Abstract translation: 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US20130229780A1

公开(公告)日：2013-09-05

申请号：US13409769

申请日：2012-03-01

Applicant: Paul Trudeau ,  Angela Ying-Ju Chen ,  William Dailey

Inventor： Paul Trudeau ,  Angela Ying-Ju Chen ,  William Dailey

IPC: H02B1/20 ,  B23P17/04

CPC classification number: H04Q1/13 ,  Y10T29/49826

Abstract: Aspects of the disclosure relate generally to a patch panel for networking components. The patch panel may facilitate access to the rear ports of the networking components. In one example, the patch panel may include a body and a face, and may mount to the networking component. Once mounted, one or more jumpers may be connected to rear ports on the component as well as connection interfaces mounted on the face of the patch panel. In this way, the rear ports may be accessible from the front of the component by the connection interfaces.

Abstract translation: 本公开的方面通常涉及用于网络组件的接线板。 接线板可以方便对网络组件的后端口的访问。 在一个示例中，接线板可以包括主体和面，并且可以安装到网络组件。 一旦安装，一个或多个跳线可以连接到组件上的后端口以及安装在接线板面上的连接接口。 以这种方式，后端口可以通过连接接口从组件的前部可访问。

公开(公告)号：US20130140706A1

公开(公告)日：2013-06-06

申请号：US13312538

申请日：2011-12-06

Applicant: Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract translation: 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。

公开(公告)号：US20130093077A1

公开(公告)日：2013-04-18

申请号：US13272540

申请日：2011-10-13

Applicant: Shih-Wei LIANG ,  Hsien-Wei CHEN ,  Ying-Ju CHEN ,  Tsung-Yuan YU ,  Mirng-Ji LII

Inventor： Shih-Wei LIANG ,  Hsien-Wei CHEN ,  Ying-Ju CHEN ,  Tsung-Yuan YU ,  Mirng-Ji LII

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/11 ,  H01L21/76841 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

Abstract translation: 半导体器件包括依次形成在半导体衬底上的钝化层，第一保护层，互连层和第二保护层。 互连层具有暴露部分，其上形成有阻挡层和焊料凸块。 钝化层，第一保护层，互连层和第二保护层中的至少一个包括形成在导电焊盘区域外的区域中的至少一个槽。

公开(公告)号：US08315607B2

公开(公告)日：2012-11-20

申请号：US12419177

申请日：2009-04-06

Applicant: Ying-Ju Chen ,  John C. Wang

Inventor： Ying-Ju Chen ,  John C. Wang

IPC: H04M3/42

CPC classification number: H04W4/14 ,  G06Q10/107 ,  H04L51/12 ,  H04L51/14 ,  H04L51/38 ,  H04M1/575 ,  H04M1/72547

Abstract: A system for managing and filtering incoming messages to a mobile device is configured to receive incoming messages using multiple formats, such as e-mail, Short Messaging System (SMS) messages, Multimedia Message System (MMS) messages, or other electronic messaging formats. One or more message filters are used to consolidate and display high importance messages by the device in a single location. The message filters may be configured to select incoming messages based on factors such as the identity of the sender and the destination account. After receiving a new message, the system compares characteristics of the incoming message to the key characteristics defined by one or more of the filters. If an incoming message matches one of the filters, the system adds the matching message to a list of high importance messages. The system provides a separate user interface to display the high importance messages.

Abstract translation: 用于管理和过滤传入消息到移动设备的系统被配置为使用诸如电子邮件，短消息系统（SMS）消息，多媒体消息系统（MMS）消息或其他电子消息格式等多种格式来接收传入消息。 一个或多个消息过滤器用于在单个位置中整合和显示设备的高重要性消息。 消息过滤器可以被配置为基于诸如发送者和目的地帐户的身份的因素来选择传入消息。 系统收到新消息后，将传入消息的特征与一个或多个过滤器定义的关键特征进行比较。 如果传入消息与其中一个过滤器匹配，则系统将匹配消息添加到高重要性消息列表中。 该系统提供单独的用户界面来显示高重要性消息。

公开(公告)号：US08278737B2

公开(公告)日：2012-10-02

申请号：US12417394

申请日：2009-04-02

Applicant: Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

Inventor： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

IPC: H01L21/00

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

Abstract translation: 提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。