发明授权
- 专利标题: High-K dielectric and metal gate stack with minimal overlap with isolation region
- 专利标题(中): 高K电介质和金属栅极堆叠与隔离区域重叠
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申请号: US13150378申请日: 2011-06-01
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公开(公告)号: US08232606B2公开(公告)日: 2012-07-31
- 发明人: Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
- 申请人: Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Hoffman Warnick LLC
- 代理商 Joseph J. Petrokaitis
- 主分类号: H01L29/76
- IPC分类号: H01L29/76
摘要:
A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.