Invention Grant
- Patent Title: Semiconductor memory write method
- Patent Title (中): 半导体存储器写入方式
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Application No.: US12621913Application Date: 2009-11-19
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Publication No.: US08243512B2Publication Date: 2012-08-14
- Inventor: Yoshihisa Watanabe
- Applicant: Yoshihisa Watanabe
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-296865 20081120
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C7/10 ; G11C7/00

Abstract:
A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage level, and a final data write operation of additionally writing final data at the threshold voltage level, includes making at least one of a write time of the preliminary data write operation, a word-line waiting time of verify read, and a bit-line waiting time of verify read, shorter than that of the final data write operation.
Public/Granted literature
- US20100124113A1 SEMICONDUCTOR MEMORY WRITE METHOD Public/Granted day:2010-05-20
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