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US08244985B2 Store performance in strongly ordered microprocessor architecture 有权
以强有序的微处理器架构存储性能

Store performance in strongly ordered microprocessor architecture
Abstract:
Apparatus and methods relating to store operations are disclosed. In one embodiment, a first storage unit is to store data. A second storage unit is to store the data only after it has become detectable by a bus agent. Moreover, the second storage unit may store an index field for each data value to be stored within the second storage unit. Other embodiments are also disclosed.
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