Invention Grant
US08254158B2 Semiconductor device having resistance based memory array and method of operation associated therewith
有权
具有基于电阻的存储器阵列的半导体器件和与其相关联的操作方法
- Patent Title: Semiconductor device having resistance based memory array and method of operation associated therewith
- Patent Title (中): 具有基于电阻的存储器阵列的半导体器件和与其相关联的操作方法
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Application No.: US12646345Application Date: 2009-12-23
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Publication No.: US08254158B2Publication Date: 2012-08-28
- Inventor: Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
- Applicant: Yong-Jun Lee , Kwangjin Lee , Taek-Sung Kim , Kwangho Kim , Wooyeong Cho , Hyunho Choi , Hye-Jin Kim , Qi Wang
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2007-0138978 20071227
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
Public/Granted literature
- US20100091553A1 SEMICONDUCTOR DEVICE HAVING RESISTANCE BASED MEMORY ARRAY AND METHOD OF OPERATION ASSOCIATED THEREWITH Public/Granted day:2010-04-15
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