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    Nonvolatile memory device and method for controlling word line or bit line thereof
    2.
    发明授权
    Nonvolatile memory device and method for controlling word line or bit line thereof 有权
    用于控制字线或其位线的非易失性存储器件和方法

    公开(公告)号：US08305806B2

    公开(公告)日：2012-11-06

    申请号：US12659690

    申请日：2010-03-17

    申请人： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    发明人： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C16/08

    摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

    摘要翻译： 非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。 本地线分别对应于全局选择线。 第一选择电路被配置为连接到全局选择线以选择全局选择线。 第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。 第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

    Method for fabricating semiconductor device
    5.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07563667B2

    公开(公告)日：2009-07-21

    申请号：US12002241

    申请日：2007-12-13

    申请人： Choul Joo Ko ,  Yong Jun Lee

    发明人： Choul Joo Ko ,  Yong Jun Lee

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/0629 ,  H01L28/40

    摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

    摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

    Method for fabricating semiconductor device
    6.
    发明申请
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20080176370A1

    公开(公告)日：2008-07-24

    申请号：US12002241

    申请日：2007-12-13

    申请人： Choul Joo Ko ,  Yong Jun Lee

    发明人： Choul Joo Ko ,  Yong Jun Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L27/0629 ,  H01L28/40

    摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

    摘要翻译： 在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。 绝缘侧壁形成在底部电极的两侧。 在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。 源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

    Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same
    10.
    发明申请
    Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
    形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法

    公开(公告)号：US20050026422A1

    公开(公告)日：2005-02-03

    申请号：US10899934

    申请日：2004-07-27

    申请人： Yoon-Hae Kim ,  Kyung-Tae Lee ,  Yong-Jun Lee

    发明人： Yoon-Hae Kim ,  Kyung-Tae Lee ,  Yong-Jun Lee

    IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02126 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

    摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.

    摘要翻译： 在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。 通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。 绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。 此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。