Invention Grant
US08261214B2 Pattern layout creation method, program product, and semiconductor device manufacturing method
有权
图案布局创建方法,程序产品和半导体器件制造方法
- Patent Title: Pattern layout creation method, program product, and semiconductor device manufacturing method
- Patent Title (中): 图案布局创建方法,程序产品和半导体器件制造方法
-
Application No.: US12630048Application Date: 2009-12-03
-
Publication No.: US08261214B2Publication Date: 2012-09-04
- Inventor: Shimon Maeda , Masahiro Miyairi , Soichi Inoue
- Applicant: Shimon Maeda , Masahiro Miyairi , Soichi Inoue
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2009-017044 20090128
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
Public/Granted literature
- US20100191357A1 PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2010-07-29
Information query