公开(公告)号：US08261214B2

公开(公告)日：2012-09-04

申请号：US12630048

申请日：2009-12-03

申请人： Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

发明人： Shimon Maeda ,  Masahiro Miyairi ,  Soichi Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.

摘要翻译： 每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于 边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的 在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图 对正确的分类结果。

公开(公告)号：US07966580B2

公开(公告)日：2011-06-21

申请号：US12186244

申请日：2008-08-05

申请人： Shimon Maeda

发明人： Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.

摘要翻译： 根据本发明的实施例的工艺模型生成方法包括：通过使形成在其上的掩模图案的测试掩模曝光来在要处理的膜上形成测试图案; 产生具有不同模型参数的多个过程模型; 通过使用每个过程模型来执行掩模图案的模拟以预测多个模型模式; 计算测试图案与每个模型图案之间的尺寸差异; 提取其中尺寸与测试图案的差异在模型范围内的模型模式; 并指定将所提取的模型模式预测为过程模型作为掩模图案。

公开(公告)号：US20090293038A1

公开(公告)日：2009-11-26

申请号：US12470334

申请日：2009-05-21

申请人： Shimon MAEDA ,  Suigen KYOH ,  Satoshi TANAKA

发明人： Shimon MAEDA ,  Suigen KYOH ,  Satoshi TANAKA

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A process proximity effect (PPE) correction method includes providing corrected cells arranged in a place/route arrangement, the corrected cells being obtained by correcting design data of a semiconductor device based on correction value for correcting PPE correction, determining whether a cell arrangement of the corrected cells is registered or not based on environmental profiles, conducting lithography verification if the corrected cells includes the cell arrangement not registered in the environmental profiles, the verification being performed on the corrected cells, wherein the corrected cell to be conducted the verification corresponds to the cell arrangement not registered, determining whether error is found or not in the verification, correcting the corrected cell to which the verification is conducted if the error is found and registering the cell arrangement in the environmental profiles, and registering the cell arrangement of the corrected cell if the error is not found.

摘要翻译： 过程接近效应（PPE）校正方法包括提供以位置/路线布置布置的校正单元，校正单元是通过基于用于校正PPE校正的校正值校正半导体器件的设计数据而获得的， 校正单元是否基于环境简档进行登记，如果校正单元包括没有注册在环境简档中的单元布置，则对校正单元执行验证，其中要进行验证的校正单元对应于 单元布置未注册，确定验证中是否存在错误，如果发现错误，则校正进行验证的修正单元，并将该单元布置注册到环境配置文件中，以及登记修正单元的单元布置 如果没有找到错误。

公开(公告)号：US20090077530A1

公开(公告)日：2009-03-19

申请号：US12269705

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

公开(公告)号：US20090077529A1

公开(公告)日：2009-03-19

申请号：US12269687

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US08785329B2

公开(公告)日：2014-07-22

申请号：US13728495

申请日：2012-12-27

申请人： Shimon Maeda ,  Kenji Konomi

发明人： Shimon Maeda ,  Kenji Konomi

IPC分类号： H01L21/00

CPC分类号： H01L21/02318 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0271 ,  H01L21/32139

摘要： In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.

摘要翻译： 在根据实施例的形成图案的方法中，在基底上形成用于DSA材料的诱导自组织的第一引导图案和第二引导图案。 在第一DSA条件下，形成相对于第一引导图案具有规则性的第一相分离图案，并且通过处理下层侧形成第一图案。 随后，在第二DSA条件下，形成相对于第二引导图案具有规则性的第二相分离图案，并且通过处理下层侧形成第二图案。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

申请人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

发明人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

摘要翻译： 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US07949967B2

公开(公告)日：2011-05-24

申请号：US12269705

申请日：2008-11-12

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此。

公开(公告)号：US07917871B2

公开(公告)日：2011-03-29

申请号：US12180244

申请日：2008-07-25

申请人： Sachiko Kobayashi ,  Suigen Kyoh ,  Shimon Maeda

发明人： Sachiko Kobayashi ,  Suigen Kyoh ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

摘要翻译： 本发明的一个方式的图形数据生成方法，该方法包括创建至少一个修改指南，以修改包含在图案数据中的修改目标点，基于评估项目评估修改指南，评估项目是 基于修改引导引起的修改目标点的图案数据的形状的改变或根据图案数据形成的图案的电特性的变化，从修改引导件中选择预定的修改指南 修改指南的评估结果的基础，以及根据所选择的修改指南修改修改目标点。

公开(公告)号：US20100153905A1

公开(公告)日：2010-06-17

申请号：US12630643

申请日：2009-12-03

申请人： Shimon MAEDA

发明人： Shimon MAEDA

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/00 ,  G03F1/26 ,  G03F1/70

摘要： A graph is created in which mask patterns adjacent to one another at a distance in which desired printing resolution cannot be obtained in a lithography process among mask patterns generated based on a pattern layout design drawing are set as nodes connected to one another by edges. An odd number loop formed by an odd number of nodes is selected from closed loops. When the selected odd number loop is not isolated, based on whether a closed loop group in which a plurality of closed loops including the odd number loop are connected includes an even number loop formed by an even number of nodes, rearrangement target nodes are selected from the odd number loop included in the closed loop group according to different selection references. The layout of patterns described in the pattern layout design drawing is rearranged corresponding to the selected rearrangement target nodes.

摘要翻译： 创建图形，其中以基于图案布局设计图形生成的掩模图案之间的光刻处理中在距离不相等的距离处彼此相邻的掩模图案被设置为通过边缘彼此连接的节点。 从闭环中选择由奇数个节点形成的奇数循环。 当所选择的奇数循环不被隔离时，基于其中包括奇数循环的多个闭环的闭环组是否包括由偶数个节点形成的偶数循环，重排目标节点从 根据不同的选择参考，包括在闭环组中的奇数循环。 在图案布局设计图中描述的图案的布局对应于所选择的重排目标节点重新排列。