发明授权
US08264388B1 Frequency integrator with digital phase error message for phase-locked loop applications
有权
具有锁相环应用的数字相位误差信号的频率积分器
- 专利标题： Frequency integrator with digital phase error message for phase-locked loop applications
- 专利标题（中）： 具有锁相环应用的数字相位误差信号的频率积分器
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申请号： US12899500申请日： 2010-10-06
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公开(公告)号： US08264388B1公开(公告)日： 2012-09-11
- 发明人: Hanan Cohen , Simon Pang
- 申请人： Hanan Cohen , Simon Pang
- 申请人地址： US CA San Diego
- 专利权人： Applied Micro Circuits Corporation
- 当前专利权人： Applied Micro Circuits Corporation
- 当前专利权人地址： US CA San Diego
- 代理机构： Law Office of Gerald Maliszewski
- 代理商 Gerald Maliszewski
- 主分类号： H03M1/48
- IPC分类号： H03M1/48
摘要：
A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
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