利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.021 秒)

    Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference
    1.
    发明授权
    Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference 有权
    使用抖动衰减时钟的发射器和接收器，该时钟源从有间隙时钟参考

    公开(公告)号：US08855258B1

    公开(公告)日：2014-10-07

    申请号：US13250794

    申请日：2011-09-30

    申请人： Viet Do ,  Simon Pang

    发明人： Viet Do ,  Simon Pang

    IPC分类号： H04L7/00

    CPC分类号： H04L7/033 ,  H04J3/076

    摘要： A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

    摘要翻译： 提供了一种系统和方法，用于使用从异步间隔时钟导出的抖动衰减时钟重新同步传输信号。 先进先出（FIFO）存储器接收从具有第一频率的第一时钟导出的异步间隔时钟。 间隔时钟的平均第二频率小于第一频率。 数据的输入串行流以响应于有间隙的时钟的速率加载。 对于有间隙的时钟进行迭代计算动态分子（DN）和动态分母（DD），得到平均分子（A和平均分母（AD）），第一个频率乘以AN / AD 创建具有第二频率的抖动衰减的第二时钟，FIFO存储器接受抖动衰减的第二时钟并以第二频率从存储器提供数据，成帧器接收来自FIFO存储器的数据和抖动衰减的第二时钟。

    Frequency integrator with digital phase error message for phase-locked loop applications
    2.
    发明授权
    Frequency integrator with digital phase error message for phase-locked loop applications 有权
    具有锁相环应用的数字相位误差信号的频率积分器

    公开(公告)号：US08264388B1

    公开(公告)日：2012-09-11

    申请号：US12899500

    申请日：2010-10-06

    申请人： Hanan Cohen ,  Simon Pang

    发明人： Hanan Cohen ,  Simon Pang

    IPC分类号： H03M1/48

    CPC分类号： H03L7/081 ,  H03L7/093 ,  H03L2207/50

    摘要： A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

    摘要翻译： 提供数字锁相环（DPLL），支持数字频率积分器和方法，用于导出DPLL中的数字相位误差信号。 数字频率积分器周期性地接收来自表示参考时钟（Tref）周期与合成器时钟（Tdco）周期的测量比率的时间数字转换器（TDC））的数字tdcOUT消息。 也接受选择第一比率（Nf）的数字消息。 作为响应，周期性地提供与参考时钟和（合成器时钟* Nf）之间的相位误差成比例的数字相位误差（pherr）消息。

    Lock detection using a digital phase error message
    3.
    发明授权
    Lock detection using a digital phase error message 有权
    使用数字相位错误消息进行锁定检测

    公开(公告)号：US08248106B1

    公开(公告)日：2012-08-21

    申请号：US12949427

    申请日：2010-11-18

    申请人： Hanan Cohen ,  Simon Pang

    发明人： Hanan Cohen ,  Simon Pang

    IPC分类号： G01R23/02

    CPC分类号： H03L7/081 ,  H03L7/095 ,  H03L7/16

    摘要： A system and method are provided for frequency lock detection using a digital phase error. A lock detection module accepts a digital phase error (pherr) message proportional to an error in phase between a reference clock and a (synthesizer clock*Nf). Also accepted is a unitless frequency error tolerance value (Δf). The lock detection module periodically supplies a lock detect signal, indicating whether the synthesizer clock frequency is within the frequency error tolerance value of the reference clock frequency.

    摘要翻译： 提供了一种使用数字相位误差进行频率锁定检测的系统和方法。 锁定检测模块接受与参考时钟和（合成器时钟* Nf）之间的相位误差成比例的数字相位误差（pherr）消息。 也接受无单位频率容差值（＆Dgr; f）。 锁定检测模块周期性地提供锁定检测信号，指示合成器时钟频率是否在参考时钟频率的频率容差值内。

    Frequency lock detection
    4.
    发明授权
    Frequency lock detection 有权
    频锁检测

    公开(公告)号：US08059774B2

    公开(公告)日：2011-11-15

    申请号：US12129477

    申请日：2008-05-29

    申请人： Shyang Kye Kong ,  Simon Pang ,  Philip Michael Clovis

    发明人： Shyang Kye Kong ,  Simon Pang ,  Philip Michael Clovis

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0004 ,  H03L7/095 ,  H03L7/113 ,  H04L7/033

    摘要： A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data signaling frequency to a synthesized signal frequency. In response to the comparing, a difference signal pulse is generated. More explicitly, the difference signal is generated at a rate responsive to the difference between the input data signaling frequency and the synthesized signal frequency. The method counts synthesized signal pulses occurring simultaneously with the difference signal pulse. If the counted synthesized signal pulses exceed a threshold (before the disappearance of the difference signal pulse), it is determined that the input data signaling frequency is about equal to the synthesized signal frequency, and a lock signal is generated.

    摘要翻译： 提供一种用于检测非同步通信接收机中的合成信号的频率获取的系统和方法。 该方法接受具有输入数据信令频率的非同步通信信号，并将输入数据信令频率与合成信号频率进行比较。 响应于比较，产生差分信号脉冲。 更明确地说，差分信号以响应于输入数据信号频率和合成信号频率之差的速率产生。 该方法对与差分信号脉冲同时出现的合成信号脉冲进行计数。 如果计数的合成信号脉冲超过阈值（在差信号脉冲消失之前），则确定输入数据信令频率大约等于合成信号频率，并产生锁定信号。

    Auto frequency acquisition maintenance in a clock and data recovery device
    7.
    发明授权
    Auto frequency acquisition maintenance in a clock and data recovery device 有权
    自动频率采集维护在时钟和数据恢复设备中

    公开(公告)号：US08111785B2

    公开(公告)日：2012-02-07

    申请号：US12372946

    申请日：2009-02-18

    申请人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

    发明人： Viet Linh Do ,  Philip Michael Clovis ,  Michael Hellmer ,  Mehmet Mustafa Eker ,  Hongming An ,  Simon Pang

    IPC分类号： H03D3/18 ,  H03D3/24 ,  H04L7/00

    CPC分类号： H04L7/0331 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/113 ,  H03L7/1976 ,  H04L7/0004

    摘要： A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

    摘要翻译： 提供了一种用于时钟和数据恢复（CDR）设备中的自动频率采集维护的系统和方法。 在自动频率采集（AFA）模式中，该方法使用相位检测器（PHD）来获取具有初始第一频率的非同步输入通信信号的相位。 在信号失去锁定/丢失（LOL / LOS）信号被断言的情况下，从存储器检索频率比值。 使用相位频率检测器（PFD），参考信号和频率比值，产生合成信号。 响应于使用PFD产生合成信号并且LOL / LOS信号被无效，旋转频率检测器（RFD）用于产生具有等于输入通信信号频率的频率的合成信号。 随着LOL / LOS信号的持续消除，PHD被使能，并且获取输入信号的相位。

    Frequency lock detection
    8.
    发明申请
    Frequency lock detection 有权
    频锁检测

    公开(公告)号：US20090296857A1

    公开(公告)日：2009-12-03

    申请号：US12129477

    申请日：2008-05-29

    申请人： Shyang Kye Kong ,  Simon Pang ,  Philip Michael Clovis

    发明人： Shyang Kye Kong ,  Simon Pang ,  Philip Michael Clovis

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0004 ,  H03L7/095 ,  H03L7/113 ,  H04L7/033

    摘要： A system and method are provided for detecting the frequency acquisition of a synthesized signal in a non-synchronous communications receiver. The method accepts a non-synchronous communication signal having an input data signaling frequency, and compares the input data signaling frequency to a synthesized signal frequency. In response to the comparing, a difference signal pulse is generated. More explicitly, the difference signal is generated at a rate responsive to the difference between the input data signaling frequency and the synthesized signal frequency. The method counts synthesized signal pulses occurring simultaneously with the difference signal pulse. If the counted synthesized signal pulses exceed a threshold (before the disappearance of the difference signal pulse), it is determined that the input data signaling frequency is about equal to the synthesized signal frequency, and a lock signal is generated.

    摘要翻译： 提供一种用于检测非同步通信接收机中的合成信号的频率获取的系统和方法。 该方法接受具有输入数据信令频率的非同步通信信号，并将输入数据信令频率与合成信号频率进行比较。 响应于比较，产生差分信号脉冲。 更明确地说，差分信号以响应于输入数据信号频率和合成信号频率之差的速率产生。 该方法对与差分信号脉冲同时出现的合成信号脉冲进行计数。 如果计数的合成信号脉冲超过阈值（在差信号脉冲消失之前），则确定输入数据信令频率大约等于合成信号频率，并产生锁定信号。

    Frequency Lock Stability in Device Using Overlapping VCO Bands
    9.
    发明申请
    Frequency Lock Stability in Device Using Overlapping VCO Bands 有权
    使用重叠VCO频带的设备中的频率锁定稳定性

    公开(公告)号：US20090147904A1

    公开(公告)日：2009-06-11

    申请号：US12388024

    申请日：2009-02-18

    申请人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    发明人： Viet Linh Do ,  Mehmet Mustafa Eker ,  Simon Pang

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0004 ,  H03L7/0891 ,  H03L7/113 ,  H03L7/1976 ,  H04L7/033

    摘要： A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

    摘要翻译： 提供了一种用于使用重叠压控振荡器（VCO）频带的接收机中的频率锁定稳定性的系统和方法。 接受输入通信信号并选择初始VCO。 使用锁相环（PLL）和初始VCO，获取输入通信信号的频率，并测量初始VCO的采集信号调谐电压。 然后，初始VCO被分离并且多个相邻频带VCO被顺序地接合。 测量每个VCO的获取的信号调谐电压，并且选择能够使用最接近预定调谐电压范围的中点的获取的信号调谐电压来产生输入通信信号频率的最终VCO。

    False frequency lock detector
    10.
    发明申请
    False frequency lock detector 有权
    虚拟锁定检测器

    公开(公告)号：US20090122935A1

    公开(公告)日：2009-05-14

    申请号：US11983675

    申请日：2007-11-09

    申请人： Simon Pang ,  Viet Linh Do ,  Mehmet Mustafa Eker

    发明人： Simon Pang ,  Viet Linh Do ,  Mehmet Mustafa Eker

    IPC分类号： H04L7/02

    CPC分类号： H04L7/0083 ,  H03L7/095 ,  H03L2207/14 ,  Y10S331/02

    摘要： A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.

    摘要翻译： 提供了用于检测时钟和数据恢复（CDR）设备中的假时钟频率锁定的系统和方法。 该方法以第一速率接收数字原始数据信号，并计算原始数据信号中的边沿转换，创建原始计数。 时钟信号也以第二速率被接受。 时钟信号是从原始数据信号恢复的定时参考。 原始数据信号以响应于时钟信号的速率被采样，产生采样信号。 在采样信号中计数边沿转换，创建采样计数。 然后，将原始计数与采样计数进行比较，以确定第一速率是否等于第二速率。 该方法用于确定第二速率是否小于第一速率 - 以检测时钟信号是否被错误地锁定到第一速率。