Invention Grant
US08268683B2 Method for reducing interfacial layer thickness for high-K and metal gate stack
有权
降低高K和金属栅极叠层的界面层厚度的方法
- Patent Title: Method for reducing interfacial layer thickness for high-K and metal gate stack
- Patent Title (中): 降低高K和金属栅极叠层的界面层厚度的方法
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Application No.: US12782859Application Date: 2010-05-19
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Publication No.: US08268683B2Publication Date: 2012-09-18
- Inventor: Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
- Applicant: Liang-Gi Yao , Chun-Hu Cheng , Chen-Yi Lee , Jeff J. Xu , Clement Hsingjen Wann
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L21/8249
- IPC: H01L21/8249

Abstract:
A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.
Public/Granted literature
- US20100317184A1 METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK Public/Granted day:2010-12-16
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