发明授权
- 专利标题: Method of calculating gate delay based on crosstalk effect due to capacitive coupling
- 专利标题(中): 基于电容耦合的串扰效应计算门延迟的方法
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申请号: US12475544申请日: 2009-05-31
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公开(公告)号: US08271255B2公开(公告)日: 2012-09-18
- 发明人: Tae II Bae , Young Hwan Kim , Jinwook Kim
- 申请人: Tae II Bae , Young Hwan Kim , Jinwook Kim
- 申请人地址: KR Pohang
- 专利权人: Postech Academy-Industry Foundation
- 当前专利权人: Postech Academy-Industry Foundation
- 当前专利权人地址: KR Pohang
- 代理机构: Kile Park Goekjian Reed & McManus PLLC
- 优先权: KR10-2009-0045655 20090525
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/455 ; G06G7/62
摘要:
Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.
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