公开(公告)号：US08271255B2

公开(公告)日：2012-09-18

申请号：US12475544

申请日：2009-05-31

申请人： Tae II Bae ,  Young Hwan Kim ,  Jinwook Kim

发明人： Tae II Bae ,  Young Hwan Kim ,  Jinwook Kim

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06G7/62

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.

摘要翻译： 提供了一种精确计算由于相邻导线之间的电容耦合引起的串扰效应驱动容性负载和噪声电流源的数字集成电路（IC）中的栅极的延迟的方法，该方法计算延迟 通过使用将通过使用通过使用数字IC的输入和输出电压值产生的栅极输出电阻库生成的线性时变输出电阻模型的输出波形和修改的戴维南当量的输出波形相加的输出波形的栅极 门的模型。