发明授权
US08274829B2 Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS
失效
行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
- 专利标题： Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS
- 专利标题（中）： 行解码器和源解码器结构适用于在+/- 10V BVDS以下操作的NOR型闪存的页面，扇区和芯片单元中的擦除
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申请号： US12455936申请日： 2009-06-09
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公开(公告)号： US08274829B2公开(公告)日： 2012-09-25
- 发明人: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人： Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人地址： US CA San Jose
- 专利权人： Aplus Flash Technology, Inc.
- 当前专利权人： Aplus Flash Technology, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Saile Ackerman LLC
- 代理商 Stephen B. Ackerman; Billy Knowles
- 主分类号： G11C11/34
- IPC分类号： G11C11/34 ; G11C11/4193
摘要：
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.
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