Invention Grant
- Patent Title: Semiconductor heterostructures to reduce short channel effects
- Patent Title (中): 半导体异质结构减少短路效应
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Application No.: US12058101Application Date: 2008-03-28
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Publication No.: US08278687B2Publication Date: 2012-10-02
- Inventor: Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
- Applicant: Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Cool Patent, P.C.
- Agent Joseph P. Curtin
- Main IPC: H01L29/778
- IPC: H01L29/778

Abstract:
Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.
Public/Granted literature
- US20090242873A1 SEMICONDUCTOR HETEROSTRUCTURES TO REDUCE SHORT CHANNEL EFFECTS Public/Granted day:2009-10-01
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