A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.