Invention Grant
- Patent Title: Fabrication of through-silicon vias on silicon wafers
- Patent Title (中): 在硅晶片上制造通硅通孔
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Application No.: US12978129Application Date: 2010-12-23
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Publication No.: US08283237B2Publication Date: 2012-10-09
- Inventor: Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
- Applicant: Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Janah & Associates, P.C.
- Agent Ashok K. Janah
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/4763 ; H01L21/44 ; H01L21/31

Abstract:
A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
Public/Granted literature
- US20120164827A1 FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS Public/Granted day:2012-06-28
Information query
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