Invention Grant
- Patent Title: Architecture incorporating configurable controller for reducing on chip power leakage
- Patent Title (中): 结合可配置的控制器来降低芯片上的功率泄漏
-
Application No.: US13096125Application Date: 2011-04-28
-
Publication No.: US08286012B2Publication Date: 2012-10-09
- Inventor: Satinder Singh Malhi , Arant Agrawal
- Applicant: Satinder Singh Malhi , Arant Agrawal
- Applicant Address: IN Greater Noida
- Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee Address: IN Greater Noida
- Agency: Hogan Lovells US LLP
- Priority: IN667/DEL/2007 20070326
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/26

Abstract:
The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
Public/Granted literature
- US20110202782A1 ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE Public/Granted day:2011-08-18
Information query