A method for manufacturing a thin film transistor array panel is disclosed. A gate wiring pattern is formed on an insulating substrate. A gate insulating layer is formed on the gate wiring pattern. A semiconductor pattern is formed on the gate insulating layer. A transparent conductive layer is formed on the gate insulating layer. The transparent conductive layer is patterned to form a pixel electrode. An opening is formed at a circumference of the pixel electrode. The opening minimizes misalignment during the manufacturing process and prevents shorts between a data line and the pixel electrode.