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    Thin film transistor array panel for a liquid crystal display
    2.
    发明授权
    Thin film transistor array panel for a liquid crystal display 有权
    用于液晶显示器的薄膜晶体管阵列面板

    公开(公告)号：US06900854B1

    公开(公告)日：2005-05-31

    申请号：US10626617

    申请日：2003-07-25

    申请人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

    发明人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

    IPC分类号： G02F1/13 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L29/10 ,  H01L29/12

    CPC分类号： G02F1/134336 ,  G02F1/1362 ,  G02F1/136286 ,  G02F2001/13606 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/12

    摘要： A gate wire including a gate line extending in the horizontal direction, and a gate electrode is formed on an insulating substrate. A gate insulating layer is formed on the gate wire and covers the same. A semiconductor pattern is formed on the gate insulating layer 30, and formed on the semiconductor pattern are a data wire having a date line in the vertical direction, a source electrode, a drain electrode separated from the source electrode opposite the source electrode with respect to the gate electrode, and an align pattern located on both sides of the data line. A passivation layer is formed on the data wire and the align pattern, and has contact holes exposing the drain electrode and an opening exposing the substrate between the data line and the align pattern. Here, the align pattern adjacent to the data line is exposed through the opening, and the semiconductor pattern and the gate insulating layer are under-cut. A pixel electrode connected to the drain electrode through the contact hole is formed on the passivation layer. Here, the opening is located between the data line and the pixel electrode. In this structure, misalignment occurring in the manufacturing process of a thin film transistor panel for a liquid crystal display is minimized, and stitch defects are prevented by uniformity forming a coupling capacitance between the data line and the pixel electrode. Shorts between the data line and the pixel electrode are prevented by forming the opening between the data line and the pixel electrode.

    摘要翻译： 包括在水平方向延伸的栅极线的栅极线和在绝缘基板上形成栅电极。 栅极绝缘层形成在栅极导线上并覆盖其上。 在栅极绝缘层30上形成半导体图案，在半导体图案上形成有在垂直方向上具有日期线的数据线，源电极，与源电极相对的源电极分离的漏电极相对于 栅极电极和位于数据线两侧的对准图案。 在数据线和对准图案上形成钝化层，并且具有暴露漏电极的接触孔和在数据线和对准图案之间暴露衬底的开口。 这里，与数据线相邻的对准图案通过开口露出，并且半导体图案和栅极绝缘层被切割。 通过接触孔连接到漏电极的像素电极形成在钝化层上。 这里，开口位于数据线和像素电极之间。 在这种结构中，在用于液晶显示器的薄膜晶体管面板的制造过程中发生的偏移被最小化，并且通过在数据线和像素电极之间形成耦合电容的均匀性来防止缝合缺陷。 通过在数据线和像素电极之间形成开口来防止数据线与像素电极之间的短路。

    Thin film transistor array panel for liquid crystal display and method of manufacturing the same
    10.
    发明授权
    Thin film transistor array panel for liquid crystal display and method of manufacturing the same 有权
    用于液晶显示器的薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US06798442B1

    公开(公告)日：2004-09-28

    申请号：US09450333

    申请日：1999-11-29

    申请人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

    发明人： Dong-Gyu Kim ,  Jun-Ho Song ,  Jong-Woong Chang ,  Jae-Ho Choi ,  Byoung-Sun Na ,  Young-Bae Park ,  Sung-Wook Huh

    IPC分类号： B02F11336

    CPC分类号： G02F1/136286 ,  G02F2001/136295 ,  H01L27/124

    摘要： A gate wire including a gate line extending in the horizontal direction, and a gate electrode is formed on an insulating substrate. A gate insulating layer is formed on the gate wire and covers the same. A semiconductor pattern is formed on the gate insulating layer 30, and formed on the semiconductor pattern are a data wire having a data line in the vertical direction, a source electrode, a drain electrode separated from the source electrode opposite the source electrode with respect to the gate electrode, and an align pattern located on both sides of the data line. A passivation layer is formed on the data wire and the align pattern, and has contact holes exposing the drain electrode and an opening exposing the substrate between the data line and the align pattern. Here, the align pattern adjacent to the data line is exposed through the opening, and the semiconductor pattern and the gate insulating layer are under-cut. A pixel electrode connected to the drain electrode through the contact hole is formed on the passivation layer. Here, the opening is located between the data line and the pixel electrode. In this structure, misalignment occurring in the manufacturing process of a thin film transistor panel for a liquid crystal display is minimized, and stitch defects are prevented by uniformly forming a coupling capacitance between the data line and the pixel electrode. Shorts between the data line and the pixel electrode are prevented by forming the opening between the data line and the pixel electrode.

    摘要翻译： 包括在水平方向延伸的栅极线的栅极线和在绝缘基板上形成栅电极。 栅极绝缘层形成在栅极导线上并覆盖其上。 在栅极绝缘层30上形成半导体图案，在半导体图案上形成有在垂直方向上具有数据线的数据线，源电极，与源极相对的源电极分离的漏电极相对于 栅极电极和位于数据线两侧的对准图案。 在数据线和对准图案上形成钝化层，并且具有暴露漏电极的接触孔和在数据线和对准图案之间暴露衬底的开口。 这里，与数据线相邻的对准图案通过开口露出，并且半导体图案和栅极绝缘层被切割。 通过接触孔连接到漏电极的像素电极形成在钝化层上。 这里，开口位于数据线和像素电极之间。 在这种结构中，在用于液晶显示器的薄膜晶体管面板的制造过程中发生的偏移被最小化，并且通过在数据线和像素电极之间均匀地形成耦合电容来防止缝合缺陷。 通过在数据线和像素电极之间形成开口来防止数据线与像素电极之间的短路。