A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.