公开(公告)号：US20140050020A1

公开(公告)日：2014-02-20

申请号：US13931275

申请日：2013-06-28

Applicant: Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

Inventor： Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

IPC: G11C11/16

CPC classification number: G11C11/1653 ,  G11C7/1054 ,  G11C7/1081 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.

Abstract translation: 提供了包括列解码器，多个子单元块和位线选择电路的半导体存储器件。 列解码器被配置为解码列地址并驱动列选择信号。 每个子单元块包括多个位线，多个字线和连接到多个位线和多个字线的多个存储单元。 位线选择电路包括多个位线连接控制器，并且被配置为响应于列选择信号选择一个或多个位线。 每个位线连接控制器分别响应于列选择信号的第一和第二列选择信号将相应的第一位线电耦合到相应的第一和第二本地输入/输出（I / O）线。

公开(公告)号：US20110075499A1

公开(公告)日：2011-03-31

申请号：US12894246

申请日：2010-09-30

Applicant: Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

Inventor： Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

IPC: G11C7/06

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

Abstract translation: 一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。 第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。 第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。 第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。 第一列选择器和第二列选择器彼此直接相邻地形成。

公开(公告)号：US08295111B2

公开(公告)日：2012-10-23

申请号：US12894246

申请日：2010-09-30

Applicant: Jae-Young Lee ,  Jung-Hwa Lee ,  Bong-Jin Kang

Inventor： Jae-Young Lee ,  Jung-Hwa Lee ,  Bong-Jin Kang

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

Abstract translation: 一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。 第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。 第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。 第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。 第一列选择器和第二列选择器彼此直接相邻地形成。