发明授权
- 专利标题： Reducing simultaneous switching noise in an integrated circuit design during placement
- 专利标题（中）： 放置期间降低集成电路设计中的同时开关噪声
-
申请号： US12557798申请日： 2009-09-11
-
公开(公告)号： US08302058B1公开(公告)日： 2012-10-30
- 发明人: Michael Howard Kipper , Joshua David Fender , Navid Azizi
- 申请人： Michael Howard Kipper , Joshua David Fender , Navid Azizi
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Womble Carlyle Sandridge & Rice, LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Methods, computer programs, and Integrated Circuits (IC) for minimizing Simultaneous Switching Noise (SSN) in the design of an IC are presented. In one embodiment, the method includes moving a candidate pin of the IC in an initial input/output (I/O) layout to create a candidate I/O layout. Further, in one operation the method calculates a first performance cost for the initial I/O layout and a second performance cost for the candidate I/O layout. The first and the second performance costs are based on an SSN cost for the initial layout and on an SSN cost for the candidate layout respectively. The method selects the layout to design the IC that has the lowest performance cost. The method operations are performed during the placement phase of an IC Computer Aided Design (CAD) tool.
信息查询
