A class D amplifier is configured to accept a digital input signal wherein the control loop of the class D amplifier employs a hybrid filter merged with the front-end of a sigma-delta ADC converter. The term hybrid refers to the filter using both digital and analog components in which the digital delay elements serve as shift registers while the filter coefficients are analog. The filter converts the digital PDM data into a step-wise sinusoidal signal. The sigma-delta ADC receiving a feedback signal subtracts the step-wise sinusoidal signal from the continuous sinusoidal signal and converts the result to a digital PDM signal, without decimation, which passes through a digital filter, a PWM generator, and a pre-driver, to provide power to the load.