Invention Grant
- Patent Title: Structure for electrostatic discharge in embedded wafer level packages
- Patent Title (中): 嵌入式晶圆级封装中的静电放电结构
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Application No.: US11746936Application Date: 2007-05-10
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Publication No.: US08309454B2Publication Date: 2012-11-13
- Inventor: Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
- Applicant: Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
- Applicant Address: DE Neubiberg
- Assignee: Intel Mobile Communications GmbH
- Current Assignee: Intel Mobile Communications GmbH
- Current Assignee Address: DE Neubiberg
- Agency: Edell, Shapiro & Finnan, LLC
- Priority: DE102007020656 20070430
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
Public/Granted literature
- US20080265421A1 Structure for Electrostatic Discharge in Embedded Wafer Level Packages Public/Granted day:2008-10-30
Information query
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