发明授权
- 专利标题: Stacked integrated circuit package having recessed sidewalls
- 专利标题(中): 具有凹陷侧壁的堆叠集成电路封装
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申请号: US13359047申请日: 2012-01-26
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公开(公告)号: US08319329B2公开(公告)日: 2012-11-27
- 发明人: Pil-kyu Kang , Jung-Ho Kim , Jong-Wook Lee , Seung-woo Choi , Dae-Lok Bae
- 申请人: Pil-kyu Kang , Jung-Ho Kim , Jong-Wook Lee , Seung-woo Choi , Dae-Lok Bae
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Myers Bigel Sibley & Sajovec, P.A.
- 优先权: KR10-2008-0107855 20081031
- 主分类号: H01L23/02
- IPC分类号: H01L23/02 ; H01L29/40 ; H01L23/053 ; H01L23/12 ; H01L23/34 ; H01L23/48 ; H01L23/52
摘要:
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
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